simplespi_s.vhdl

Serial pheripheral master

-------------------------------------------------------------------------------
-- Title      : "SPI Slave"
-- Project    : 
-------------------------------------------------------------------------------
-- File       : simpleSPI_S.vhdl
-- Author     : Tom Scott www.missiontech.co.nz
-- Company    : Mission Technologies        
-- Created    : 2007-02-05
-- Last update: 2007-05-21
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: Creates a simple SPI Slave
-------------------------------------------------------------------------------
-- Copyright (c) 2007 Mission Technologies
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2007-05-10  1.0      toms    Created
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-------------------------------------------------------------------------------
entity simpleSPI_S is
  port (
    reset    : in  std_logic;
    clk      : in  std_logic;
    SCLK     : in std_logic;
    SS       : in std_logic;
    MOSI     : in  std_logic;
    MISO     : out std_logic;
    DataToTx : in std_logic_vector(15 downto 0);
    DataRxd  : out std_logic_vector(15 downto 0)
    );
end simpleSPI_S;

architecture a of simpleSPI_S is
    type state_type is (idle, rxBit, inc_index);
    signal state : state_type;
    signal SCLK_old : std_logic;
    signal SS_old : std_logic;
begin
  process(clk, reset, SS, SCLK)
    variable index : integer range 0 to 120;
    variable RxdData : std_logic_vector(15 downto 0);
    variable TxData : std_logic_vector(15 downto 0);
    variable MISO_s : std_logic;

 begin
    if reset = '1' then
      RxdData := (others => '0');  
      index := 0;
      TxData := DataToTx;
      MISO_s := 'Z';
      SCLK_old <= 'Z';
      SS_old <= 'Z';
    else
      if(clk'event and clk = '1') then
         SCLK_old <= SCLK;
         SS_old <= SS;
         TxData := DataToTx;
       -- if SS goes low then driven from Master
       -- detect falling edge
       -- make first bit available for Master
         if SS_old = '1' and SS = '0' then
           MISO_s := TxData(index);    -- data out from slave
         elsif(SS = '1') then
           index := 0;
           MISO_s := 'Z';
         end if;
           

       -- on rising edge of SCLK grab data from MOSI
         if(SCLK_old = '0' and SCLK = '1') then 
           RxdData(index) := MOSI;     -- data in from master

       -- on falling edge of SCLK place next data on MISO
         elsif(SCLK_old = '1'and SCLK = '0') then  
           index := index + 1;
           MISO_s := DataToTx(index);    -- data out from slave
         end if;
      end if;
    end if;     
    DataRxd <= RxdData;
    MISO <= MISO_s;
  end process;
end a;