p8-72.sp

《CMOS电路模拟与设计——基于Hspice》——电路设计与仿真,钟文耀, 郑美珠,科学出版社

*EXERCISE8_15  CMOS INVERTER change WorL for min TD
.options post=2 list
.PARAM Length=2u 
M1  2  1  3  3  MP  L=length W=4u
M2  2  1  0  0  MN  L=2u W=4u
VDD  3   0   DC 5V
VIN  1   0   pulse 0   5   0n   10n   10n   90n   200n
CL   2   0   0.1pF  
.MODEL MP PMOS (level=2 LD=0.250U TOX=365E-10
+ NSUB=6.193910E+15 VTO=-0.826989 KP=2.2870E-05
+ GAMMA=0.4793 PHI=0.6 U0=241.796 UEXP=0.214214
+ UCRIT=19100.4 DELTA=0.859687 VMAX=47972.9 XJ=0.250U
+ LAMBDA=5.403347E-02 NFS=2.351269E+11 NEFF=1.001
+ NSS=1.0E+12 TPG=-1.0 RSH=76.020 CGDO=3.54775E-10
+ CGSO=3.54775E-10 CGBO=6.981174E-10 CJ=2.2624E-04
+ MJ=0.46650 CJSW=2.3825E-10 MJSW=0.24660 PB=0.700)
.MODEL MN NMOS (LEVEL=2 LD=0.250U TOX=365E-10
+ NSUB=2.13818E+16 VTO=0.84898 KP=5.7790E-05
+ GAMMA=0.8905 PHI=0.6 U0=610.8 UEXP=0.244555
+ UCRIT=128615 DELTA=2.0298 VMAX=92227.9 XJ=0.250U
+ LAMBDA=1.956049E-02 NFS=2.307838E+12 NEFF=1
+ NSS=1.0E+12 TPG=1.0 RSH=22.730 CGDO=3.54775E-10
+ CGSO=3.54775E-10 CGBO=6.354506E-10 CJ=3.7740E-04
+ MJ=0.45890 CJSW=5.1360E-10 MJSW=0.36620 PB=0.800)
.TRAN  1n   1u  SWEEP length 2u  10u   0.5u
.MEAS TRAN vmax1 MAX V(1) FROM 150n TO 250n
.MEAS TRAN vmin1 MIN V(1) FROM 150n TO 250n
.MEAS TRAN vmax2 MAX V(2) FROM 150n TO 250n
.MEAS TRAN vmin2 MIN V(2) FROM 150n TO 250n
.MEAS TRAN TPHL TRIG V(1) val='0.5*(vmax1-vmin1)+vmin1'
+ TD=150ns RISE=1 TARG V(2) val='0.5*(vmax2-vmin2)+vmin2'
FALL=1
.MEAS TRAN  TPLH TRIG V(1) val='0.5*(vmax1-vmin1)+vmin1'
+ TD=150ns FALL=1 TARG V(2) val='0.5*(vmax2-vmin2)+vmin2'
RISE=1
.END