p6-13.sp

《CMOS电路模拟与设计——基于Hspice》——电路设计与仿真,钟文耀, 郑美珠,科学出版社

*HSPICE SIMULATION FILE EX6-1
*NAND GATE DELAY W/ DIFFERENT LOADING
.OPTIONS POST=2 LIST
.LIB '.\Mm0355v.l' TT
VCC VCC GND DC URAIL
vss vss gnd dc 0
va a GND pwl(0 0 4.9n 0 5n 3.3 9.9n 3.3 10n 0 14.9n 0 15n 3.3)
vb b gnd pwl(0 0 9.9n 0 10n 3.3 15n 3.3)
M1 y a vcc vcc pch w=2u l=0.7u
M2 y b vcc vcc pch w=2u l=0.7u
M3 y a a2 vss nch w=4u l=0.35u
M4 a2 b vss vss nch w=4u l=0.35u
.tran 1p 20n
.PARAM URAIL=3.3V
.MEASURE TRAN TRFDELAY TRIG V(a) VAL="URAIL/2" TD=0.01NS
+rise=1 TARG V(y) VAL="URAIL/2" fall=1
.OPTIONS POST METHOD=GEAR ACCURATE=1
.OPTIONS INGOLD=2
.END