memcfg.s

44b0迷你boot

;**************************************************************************
;NAME: MEMCFG.s
;copyright:wzz at Qingdao University 2008
;**************************************************************************
;Address define
;**************************************************************************
aBWSCON     EQU     0x01C80000
aBANKCON0   EQU     0x01C80004
aBANKCON1   EQU     0x01C80008
aBANKCON2   EQU     0x01C8000C
aBANKCON3   EQU     0x01C80010
aBANKCON4   EQU     0x01C80014
aBANKCON5   EQU     0x01C80018
aBANKCON6   EQU     0x01C8001C
aBANKCON7   EQU     0x01C80020
aREFRESH    EQU     0x01C80024
aBANKSIZE   EQU     0x01C80028
aMRSRB6     EQU     0x01C8002C
aMRSRB7     EQU     0x01C80030
;**************************************************************************
;============================================================
;BWSCON
;ST7 WS7 DW7 ST6 WS6 DW6...ST1 WS1 DW1 DW0 ENDIAN

;ST
;This bit determines SRAM for using UB/LB for bank X:
;0 = Not using UB/LB ( Pin[14:11] is dedicated nWBE[3:0] ) 
;1 = Using UB/LB ( Pin[14:11] is dedicated nBE[3:0] )

;WS
;This bit determines WAIT status for bank X:
;0 = WAIT disable, 1 = WAIT enable

;DW
;These two bits determine data bus width for bank X:
;00 = 8-bit 01 = 16-bit, 10 = 32-bit

cBWSCON16   EQU   0x01000002  ;Bank0=16bit flash
;                   ||||||--	
;                   |||||---	
;                   ||||----	
;                   |||-----
;                   ||------
;                   |-------   ;Bank6=16bit SDRAM  0x1
;                   -------- 
;**********MEMORY CONTROL PARAMETERS*******************************
;When MCLK=66MHz,1clk=0.0152us=15.2ns
;============================================================
;nGCS0-nGCS5
;Tacs [14:13] Address set-up before nGCSn
;Tcos [12:11] Chip selection set-up nOE
;Tacc [10:8]  Access cycle
;Toch [7:6]   Chip selection hold on nOE
;Tcah [5:4]   Address holding time after nGCSn
;Tpac [3:2]   Page mode access cycle @ Page mode
;PMC  [1:0]   Page mode configuration
;BANK0
B0_Tacs EQU 0x0;1clk
B0_Tcos EQU 0x0;1clk
B0_Tacc EQU 0x7;14clk
B0_Toch EQU 0x0;1clk
B0_Tcah EQU 0x0;1clk
B0_Tpac EQU 0x0;1clk
B0_PMC  EQU 0x0;normal

;============================================================
;BANK6&7
;MT [16:15] These two bits determines the memmory type
;Memory Type=Rom or SRAM MT=00
;Tacs [14:13] Address set-up before nGCSn
;Tcos [12:11] Chip selection set-up nOE
;Tacc [10:8]  Access cycle
;Toch [7:6]   Chip selection hold on nOE
;Tcah [5:4]   Address holding time after nGCSn
;Tpac [3:2]   Page mode access cycle @ Page mode
;PMC  [1:0]   Page mode configuration
;Memory Type=FP DRAM MT=01
;EDO DRAM [MT=10]
;Trcd [5:4] RAS to CAS delay
;Tcas [3]   CAS pulse width
;Tcp  [2]   CAS pre-charge
;CAN  [1:0] Column address number
;
;Bank 6(if SROM) parameter
B6_Tacs		EQU	0x3	;4clk
B6_Tcos		EQU	0x3	;4clk
B6_Tacc		EQU	0x7	;14clk
B6_Tcoh		EQU	0x3	;4clk
B6_Tah		EQU	0x3	;4clk
B6_Tacp		EQU	0x3	;6clk
B6_PMC		EQU	0x0	;normal(1data)

;Bank 7(if SROM) parameter
B7_Tacs		EQU	0x3	;4clk
B7_Tcos		EQU	0x3	;4clk
B7_Tacc		EQU	0x7	;14clk
B7_Tcoh		EQU	0x3	;4clk
B7_Tah		EQU	0x3	;4clk
B7_Tacp		EQU	0x3	;6clk
B7_PMC		EQU	0x0	;normal(1data)

;Bank 6 (if SDRAM) parameter
B6_MT		EQU	0x3	;SDRAM
B6_Trcd		EQU	0x0	;2clk
B6_SCAN		EQU	0x0	;8bit

B6_WBL		EQU 0x0
B6_TM		EQU 0x0
B6_CL		EQU 0x2
B6_BT		EQU 0x0
B6_BL		EQU 0x0

;Bank 7 (if SDRAM) parameter
B7_MT		EQU	0x3	;SDRAM
B7_Trcd		EQU	0x0	;2clk
B7_SCAN		EQU	0x0	;8bit
B7_WBL		EQU 0x0
B7_TM		EQU 0x0
B7_CL		EQU 0x2
B7_BT		EQU 0x0
B7_BL		EQU 0x0

;============================================================
;REFRESH CONTROL REGISTER
;REFEN [23] DRAM/SDRAM Refresh Enable
;TREFMD [22] DRAM/SDRAM Refresh Mode
;REFRESH parameter
REFEN		EQU	0x1	;Refresh enable
TREFMD		EQU	0x0	;CBR(CAS before RAS)/Auto refresh
Trp		    EQU	0x0	;2clk
Trc		    EQU	0x0	;4clk//
Tchr		EQU	0x2	;3clk
REFCNT		EQU	1425   ;1019	;period=15.6us, MCLK=60Mhz
;
;============================================================
;BANKSIZE register
SCLKEN		EQU 0x1;
BK76MAP		EQU	0x6;8M
;************************************************
 
 END