adcint.vhd

频率控制核心

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ADCINT IS
PORT (D: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      CLK,EOC: IN STD_LOGIC;
      ALE, START, OE, ADDA, LOCK0 : OUT STD_LOGIC;
      Q: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0));
END ADCINT;
ARCHITECTURE BHV OF ADCINT IS
TYPE STATES IS (ST0, ST1, ST2, ST3, ST4);
SIGNAL CURRENT_STATE, NEXT_STATE: STATES :=ST0;
SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL LOCK : STD_LOGIC;
BEGIN
ADDA<='1';
Q<=REGL; LOCK0<=LOCK;
COM: PROCESS(CURRENT_STATE,EOC)
BEGIN
CASE CURRENT_STATE IS
WHEN ST0 => ALE<='0';START<='0';LOCK<='0';OE<='0';NEXT_STATE<=ST1;
WHEN ST1 => ALE<='1';START<='1';LOCK<='0';OE<='0';NEXT_STATE<=ST2;
WHEN ST2 => ALE<='0';START<='0';LOCK<='0';OE<='0'; 
IF (EOC='1')THEN NEXT_STATE<=ST3; ELSE  NEXT_STATE<=ST2;
END IF;
WHEN ST3 => ALE<='0';START<='0';LOCK<='0';OE<='1';NEXT_STATE<=ST4;
WHEN ST4 => ALE<='0';START<='0';LOCK<='1';OE<='1';NEXT_STATE<=ST0;
WHEN OTHERS => NEXT_STATE<=ST0;
END CASE;
END PROCESS COM;
REG: PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1') THEN CURRENT_STATE<=NEXT_STATE;
END IF;
END PROCESS REG;
LATCH1: PROCESS(LOCK)
BEGIN
IF LOCK='1' AND LOCK'EVENT THEN REGL<=D;
END IF;
END PROCESS LATCH1;
END BHV;