tag_mem_tst.vhd

lattice tag mem 操作代码

--JTAG写入数据，逻辑读TAG数据。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library xp2;
use xp2.components.all;

entity tag_mem_tst is
port(
  --	cs_in	:in	std_logic;
	clk	:in	std_logic;
	reset	:in	std_logic;
	
	data_valid:out	std_logic;
	data_bus:out	std_logic_vector(7 downto 0);
	dataout	:out	std_logic;
  switch_s502: in std_logic_vector(7 downto 0) -- select tag memory adress
); 
end tag_mem_tst;

architecture arch_tag_mem_tst of tag_mem_tst is

--signal:
signal cs,tag_cs:std_logic;
signal dataout_t:std_logic;
signal clkp:std_logic;
signal si:std_logic;
signal counter_tag_cs:std_logic_vector(11 downto 0);
signal data_bus_valid:std_logic;
signal valid_counter:std_logic_vector(2 downto 0);
signal shifter,data_busp:std_logic_vector(7 downto 0);

--address
 signal address:std_logic_vector(7 downto 0);

-- Component declarations go in either the architecture declaration section
-- or in a package.
component tag_mem0

	port(
	-- enter port declarations here
        CLK: in  std_logic; 
        SI: in  std_logic; 
        CS: in  std_logic; 
        SO: out  std_logic);
end component;

-- parameterized module component declaration
component pll0
    port (CLK: in std_logic; CLKOP: out std_logic; LOCK: out std_logic);
end component;

begin

data_valid<=data_bus_valid;
dataout<=dataout_t;

-- Component instances go in the architecture body

-- parameterized module component instance
pll_inst0 : pll0
    port map (CLK=>clk, CLKOP=>clkp, LOCK=>open);


tag_mem_u1:tag_mem0

	port map(
	-- enter port connections here.
        CLK	=>	clkp,
        SI	=>	si,
        CS 	=>	tag_cs,
        SO	=>	dataout_t
	);
--
--read tag cs_in buffer:
--process(reset,clkp)
--begin
--	if(reset='0')then
--		cs<='1';
--	elsif(clkp'event and clkp='1')then
--		cs<=cs_in;
--	end if;
--
--end process;
cs<='0';

--tag cs gen:
process(reset,clkp)
begin
	
	if(reset='0')then
		tag_cs<='1';	
		counter_tag_cs<="000000000000";
	elsif(clkp'event and clkp='1')then
		if(cs='0' or (counter_tag_cs<2215 and counter_tag_cs>0))then
			counter_tag_cs<=counter_tag_cs+'1';
			tag_cs<='0';
		else
			tag_cs<='1';	
			counter_tag_cs<="000000000000";
		end if;
	end if;
end process;

--si_gen:read tag ":read command=0x4e=8b01001110
process(reset,clkp)
begin
	if(reset='0')then
		si<='0';
	elsif(clkp'event and clkp='1')then
		if(counter_tag_cs="000000001" or counter_tag_cs="000000100" or counter_tag_cs="000000101" or counter_tag_cs="000000110")then
			si<='1';
		else
			si<='0';
		end if;
	end if;
		
end process;

--data_bus_valid:
process(reset,clkp)
begin
	if(reset='0')then
		data_bus_valid<='0';
	elsif(clkp'event and clkp='1')then
		if(counter_tag_cs>30)then--si_command(8bit)+24
			data_bus_valid<='1';
		else
			data_bus_valid<='0';
		end if;
	end if;
end process;

--valid_counter:
process(reset,clkp)
begin
	if(reset='0')then
		valid_counter<="000";
	elsif(clkp'event and clkp='1')then
		if(data_bus_valid='1')then
			valid_counter<=valid_counter+'1';
		else
			valid_counter<="000";
		end if;
	end if;
end process;

--tag data shift and data_bus output:
process(reset,clkp)
begin
	if(reset='0')then
		shifter<="00000000";
	--	data_bus<="00000000";
		data_busp<="00000000";
	elsif(clkp'event and clkp='1')then
		if(data_bus_valid='1')then
			shifter<=shifter(6 downto 0) & dataout_t;
			if(valid_counter="000")then
				data_busp<=shifter;
			--	data_bus<=not data_busp;--LED display
			end if;
		end if;
	end if;
end process;


-- generate address <=FFH
process(reset,clkp)
begin
	  if(reset='0')then
		   address<=(others=>'0');
	  elsif rising_edge(clkp) then 
	      if (valid_counter="111") then 
	            if address="11111111" then 
	                 address<=(others=>'1');
	             else     
	             address<= address+1;
	            end if ;
	      end if ;
	   end if;      
	 end process;
	 
	 --led  display  tag memory 
	 
	process(reset,clkp)
begin
	  if(reset='0')then
		   data_bus<=(others=>'1'); 
	  elsif rising_edge(clkp) then
	        
	         if (switch_s502=address) then 
   	         data_bus<=not data_busp;
	          end if;
    end if;
	   
	   
	   end process;
	         
	         
	         
	   
end arch_tag_mem_tst;