tag_mem_tst.srf

lattice tag mem 操作代码

Synplicity HDL Compiler, version 1.0, Build 020R, built Nov  5 2008
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved

@N: CD720 :"d:\ispTOOLS7_2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@I:: "d:\ispTOOLS7_2\ispcpld\..\cae_library\synthesis\vhdl\XP2.vhd"
@I:: "E:\3\tag_mem\tag_mem.vhd"
@I:: "E:\3\tag_mem\tag_mem0.vhd"
@I:: "E:\3\tag_mem\pll0.vhd"
@I:: "E:\3\tag_mem\tag_mem_tst.vhd"
VHDL syntax check successful!
# Fri Dec 19 12:32:47 2008

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@I::"d:\ispTOOLS7_2\synpbase\lib\lucent\xp2.v"
@I::"E:\3\tag_mem\tag_mem.h"
Verilog syntax check successful!
# Fri Dec 19 12:32:47 2008

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@N: CD720 :"d:\ispTOOLS7_2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@I:: "d:\ispTOOLS7_2\ispcpld\..\cae_library\synthesis\vhdl\XP2.vhd"
@I:: "E:\3\tag_mem\tag_mem.vhd"
@I:: "E:\3\tag_mem\tag_mem0.vhd"
@I:: "E:\3\tag_mem\pll0.vhd"
@I:: "E:\3\tag_mem\tag_mem_tst.vhd"
VHDL syntax check successful!
@N: CD630 :"E:\3\tag_mem\tag_mem_tst.vhd":9:7:9:17|Synthesizing work.tag_mem_tst.arch_tag_mem_tst 
@N: CD630 :"E:\3\tag_mem\tag_mem0.vhd":14:7:14:14|Synthesizing work.tag_mem0.structure 
Post processing for work.tag_mem0.structure
@N: CD630 :"E:\3\tag_mem\pll0.vhd":14:7:14:10|Synthesizing work.pll0.structure 
Post processing for work.pll0.structure
Post processing for work.tag_mem_tst.arch_tag_mem_tst
# Fri Dec 19 12:32:47 2008

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Synplicity Netlist Filter, version 1.0, Build 020R, built Nov  5 2008
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Dec 19 12:32:47 2008

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@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Dec 19 12:32:47 2008

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Synplicity Generic Technology Mapper, Version 9.4.2, Build 061R, Built Nov 25 2008 09:10:23
Copyright (C) 1994-2008, Synplicity Inc.  All Rights Reserved
Product Version Version 9.6L1
@W: BN246 |Failed to find top level module 'work.tag_mem_tst' as specified in project file
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 

Automatic dissolve during optimization of view:work.tag_mem_tst(arch_tag_mem_tst) of tag_mem_u1(tag_mem0)
Automatic dissolve during optimization of view:work.tag_mem_tst(arch_tag_mem_tst) of pll_inst0(pll0)
Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 101MB)

@N:"e:\3\tag_mem\tag_mem_tst.vhd":171:3:171:4|Found counter in view:work.tag_mem_tst(arch_tag_mem_tst) inst address[7:0]
@N:"e:\3\tag_mem\tag_mem_tst.vhd":92:1:92:2|Found counter in view:work.tag_mem_tst(arch_tag_mem_tst) inst counter_tag_cs[11:0]
@N:"e:\3\tag_mem\tag_mem_tst.vhd":138:1:138:2|Found counter in view:work.tag_mem_tst(arch_tag_mem_tst) inst valid_counter[2:0]
@N: MF179 :"e:\3\tag_mem\tag_mem_tst.vhd":192:14:192:32|Found 8 bit by 8 bit '==' comparator, 'switch_s502_1'
Dissolving instances of view:VhdlGenLib.CMP_EQ_tag_mem_tst_w8(cell_level) before factorization cost=36, pathcnt=1
Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)



######### START OF GENERATED CLOCK OPTIMIZATION REPORT #########[

================================================================
		Instance:Pin		Generated Clock Optimization Status
================================================================
		data_bus_valid						Not Done


######### END OF GENERATED CLOCK OPTIMIZATION REPORT #########]

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)

Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)

Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		     0.64ns		  32 /        50
   2		0h:00m:01s		     0.64ns		  32 /        50
   3		0h:00m:01s		     0.64ns		  32 /        50
------------------------------------------------------------

Net buffering Report for view:work.tag_mem_tst(arch_tag_mem_tst):
No nets needed buffering.

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)

Found clock tag_mem_tst|pll_inst0.clkp_inferred_clock with period 5.00ns 
@W: MT246 :"e:\3\tag_mem\pll0.vhd":85:4:85:12|Blackbox EPLLD is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Fri Dec 19 12:32:49 2008
#


Top view:               tag_mem_tst
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: 0.634

                                              Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                                Frequency     Frequency     Period        Period        Slack     Type         Group              
------------------------------------------------------------------------------------------------------------------------------------------------
tag_mem_tst|pll_inst0.clkp_inferred_clock     200.0 MHz     229.1 MHz     5.000         4.366         0.634     inferred     Inferred_clkgroup_0
System                                        200.0 MHz     331.0 MHz     5.000         3.021         1.979     system       default_clkgroup   
================================================================================================================================================





Clock Relationships
*******************

Clocks                                                                                |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                   Ending                                     |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
tag_mem_tst|pll_inst0.clkp_inferred_clock  tag_mem_tst|pll_inst0.clkp_inferred_clock  |  5.000       0.634  |  No paths    -      |  No paths    -      |  No paths    -    
============================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port               Starting            User           Arrival     Required          
Name               Reference           Constraint     Time        Time         Slack
                   Clock                                                            
------------------------------------------------------------------------------------
clk                System (rising)     NA             0.000       3.264             
reset              NA                  NA             NA          NA           NA   
switch_s502[0]     System (rising)     NA             0.000       1.192             
switch_s502[1]     System (rising)     NA             0.000       1.192             
switch_s502[2]     System (rising)     NA             0.000       1.192             
switch_s502[3]     System (rising)     NA             0.000       1.192             
switch_s502[4]     System (rising)     NA             0.000       1.192             
switch_s502[5]     System (rising)     NA             0.000       1.192             
switch_s502[6]     System (rising)     NA             0.000       1.944             
switch_s502[7]     System (rising)     NA             0.000       1.944             
====================================================================================


Output Ports: 

Port            Starting                                               User           Arrival     Required          
Name            Reference                                              Constraint     Time        Time         Slack
                Clock                                                                                               
--------------------------------------------------------------------------------------------------------------------
data_bus[0]     tag_mem_tst|pll_inst0.clkp_inferred_clock (rising)     NA             4.187       5.000             
data_bus[1]     tag_mem_tst|pll_inst0.clkp_inferred_clock (rising)     NA             4.187       5.000             
data_bus[2]     tag_mem_tst|pll_inst0.clkp_inferred_clock (rising)     NA             4.187       5.000             
data_bus[3]     tag_mem_tst|pll_inst0.clkp_inferred_clock (rising)     NA             4.187       5.000             
data_bus[4]     tag_mem_tst|pll_inst0.clkp_inferred_clock (rising)     NA             4.187       5.000             
data_bus[5]     tag_mem_tst|pll_inst0.clkp_inferred_clock (rising)     NA             4.187       5.000             
data_bus[6]     tag_mem_tst|pll_inst0.clkp_inferred_clock (rising)     NA             4.187       5.000             
data_bus[7]     tag_mem_tst|pll_inst0.clkp_inferred_clock (rising)     NA             4.187       5.000             
data_valid      tag_mem_tst|pll_inst0.clkp_inferred_clock (rising)     NA             4.366       5.000             
dataout         System (rising)                                        NA             3.021       5.000             
====================================================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lfxp2_17e-5

Register bits: 50 of 16560 (0%)
PIC Latch:       0
I/O cells:       20


Details:
CCU2B:          15
FD1P3DX:        24
FD1S3BX:        1
FD1S3DX:        17
GSR:            1
IB:             10
INV:            9
OB:             10
OFS1P3BX:       8
ORCALUT4:       22
PUR:            1
SSPIA:          1
VHI:            1
VLO:            1
Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 101MB peak: 102MB)

Writing Analyst data base E:\3\tag_mem\tag_mem_tst.srm
@N: MF203 |Set autoconstraint_io 
Finished Writing Netlist Databases (Time elapsed 0h:00m:02s; Memory used current: 101MB peak: 102MB)

Writing EDIF Netlist and constraint files
Version 9.6L1
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:02s; Memory used current: 104MB peak: 105MB)

Writing Verilog Simulation files
Finished Writing Verilog Simulation files (Time elapsed 0h:00m:02s; Memory used current: 104MB peak: 105MB)

Writing VHDL Simulation files
Finished Writing VHDL Simulation files (Time elapsed 0h:00m:03s; Memory used current: 104MB peak: 105MB)

Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 105MB peak: 105MB)

@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design 
Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 105MB peak: 105MB)

Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 105MB peak: 105MB)

@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design 
Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:03s; Memory used current: 105MB peak: 105MB)

Mapper successful!
Process took 0h:00m:03s realtime, 0h:00m:03s cputime
# Fri Dec 19 12:32:51 2008

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