tag_mem.syn

lattice tag mem 操作代码

JDF B
// Created by Version 7.2 
PROJECT tag_mem
DESIGN tag_mem Normal
DEVKIT LFXP2-17E-5QN208C
ENTRY Mixed Verilog/VHDL
MODULE tag_mem.vhd
MODSTYLE tag_mem Normal
MODULE tag_mem0.vhd
MODSTYLE tag_mem0 Normal
MODULE pll0.vhd
MODSTYLE pll0 Normal
MODULE tag_mem_tst.vhd
MODSTYLE tag_mem_tst Normal
SYNTHESIS_TOOL Synplify
SIMULATOR_TOOL ActiveHDL
AUTO_READ_DESIGN TRUE
TOPMODULE tag_mem_tst