5_1_par.asd

lattice tag mem 操作代码

[ActiveSupport PAR]
; Global primary clocks
GLOBAL_PRIMARY_USED = 1;
; Global primary clock #0
GLOBAL_PRIMARY_0_SIGNALNAME = clkp;
GLOBAL_PRIMARY_0_DRIVERTYPE = PLL;
GLOBAL_PRIMARY_0_LOADNUM = 34;
; # of global secondary clocks
GLOBAL_SECONDARY_USED = 0;
; I/O Bank 0 Usage
BANK_0_USED = 0;
BANK_0_AVAIL = 20;
BANK_0_VCCIO = NA;
BANK_0_VREF1 = NA;
BANK_0_VREF2 = NA;
; I/O Bank 1 Usage
BANK_1_USED = 1;
BANK_1_AVAIL = 18;
BANK_1_VCCIO = NA;
BANK_1_VREF1 = NA;
BANK_1_VREF2 = NA;
; I/O Bank 2 Usage
BANK_2_USED = 2;
BANK_2_AVAIL = 18;
BANK_2_VCCIO = 3.3V;
BANK_2_VREF1 = NA;
BANK_2_VREF2 = NA;
; I/O Bank 3 Usage
BANK_3_USED = 16;
BANK_3_AVAIL = 16;
BANK_3_VCCIO = 3.3V;
BANK_3_VREF1 = NA;
BANK_3_VREF2 = NA;
; I/O Bank 4 Usage
BANK_4_USED = 0;
BANK_4_AVAIL = 18;
BANK_4_VCCIO = NA;
BANK_4_VREF1 = NA;
BANK_4_VREF2 = NA;
; I/O Bank 5 Usage
BANK_5_USED = 0;
BANK_5_AVAIL = 20;
BANK_5_VCCIO = NA;
BANK_5_VREF1 = NA;
BANK_5_VREF2 = NA;
; I/O Bank 6 Usage
BANK_6_USED = 1;
BANK_6_AVAIL = 18;
BANK_6_VCCIO = NA;
BANK_6_VREF1 = NA;
BANK_6_VREF2 = NA;
; I/O Bank 7 Usage
BANK_7_USED = 0;
BANK_7_AVAIL = 18;
BANK_7_VCCIO = NA;
BANK_7_VREF1 = NA;
BANK_7_VREF2 = NA;