5_1.par

lattice tag mem 操作代码

Lattice Place and Route Report for Design "tag_mem_map.ncd"
Fri Dec 19 12:33:16 2008

PAR: Place And Route ispLever_v72_PROD_Build (44).
Command line: d:/ispTOOLS7_2/ispfpga\bin\nt\par -f tag_mem.p2t tag_mem_map.ncd tag_mem.dir
tag_mem.prf
Preference file: tag_mem.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file tag_mem_map.ncd.
Design name: tag_mem_tst
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP2-17E
Package:     PQFP208
Speed:       5
Loading device for application par from file 'mg5a50x47.nph' in
environment: d:/ispTOOLS7_2/ispfpga.
Package: Version 1.63, Status: FINAL
Speed Hardware Data: version 7.3 (final) 
License checked out.


Ignore Preference Error(s):  True
Dumping design to file C:/DOCUME~1/www/LOCALS~1/Temp/neo_2.
Device utilization summary:

   GSR                1/1           100% used
   IOLOGIC            8/364           2% used
   PIO (prelim)      20/358           5% used
                     20/146          13% bonded
   SSPICIB            1/1           100% used
   SLICE             46/8280         <1% used



1 potential circuit loop found in timing analysis.
Number of Signals: 127
Number of Connections: 269

Pin Constraint Summary:
   18 out of 20 pins locked (90% locked).

WARNING - par: The input signal "clk_c" of PLL instance
          "pll_inst0/PLLInst_0" may not be able to use the dedicated CLKI
          input pin, therefore general routing may have to be used for this
          signal.
The following 1 signal is selected to use the primary clock routing resources:
    clkp (driver: pll_inst0/PLLInst_0, clk load #: 34)

No signal is selected as DCS clock.

No signal is selected as secondary clock.

Signal reset_c is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 19 secs 

CDP(congestion driven placement) auto mode does not turn on CDP.
	To force CDP on, set -exp parCDP=1
Starting Placer Phase 1.
Placer score = 36768.
.............................
Placer score = 17472.
Finished Placer Phase 1.  REAL time: 31 secs 

Starting Placer Phase 2.
.
Placer score =  16315
Finished Placer Phase 2.  REAL time: 31 secs 


------------------ Clock Report ------------------

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  PLL        : 1 out of 4 (25%)
  DCS        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "clkp" from CLKOP on comp "pll_inst0/PLLInst_0" on PLL site "LLPLL", clk load = 34

  PRIMARY  : 1 out of 8 (12%)
     DCS   : 0 out of 2 (0%)
  SECONDARY: 0 out of 4 (0%)

Edge Clocks:
  No edge clock selected

--------------- End of Clock Report ---------------


I/O Usage Summary (final):
   20 out of 358 (5.6%) PIO sites used.
   20 out of 146 (13.7%) bonded PIO sites used.
   Number of PIO comps: 20; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
----------+------------------+-------+-----------------
 I/O Bank | Usage            | Vccio |  Vref1 / Vref2
----------+------------------+-------+-----------------
    0     |   0 / 20  (  0%) |    -  |      - / -     
    1     |   1 / 18  (  5%) |    -  |      - / -     
    2     |   2 / 18  ( 11%) | 3.3V  |      - / -     
    3     |  16 / 16  (100%) | 3.3V  |      - / -     
    4     |   0 / 18  (  0%) |    -  |      - / -     
    5     |   0 / 20  (  0%) |    -  |      - / -     
    6     |   1 / 18  (  5%) |    -  |      - / -     
    7     |   0 / 18  (  0%) |    -  |      - / -     
----------+------------------+-------+-----------------


DSP Utilization Summary:
-------------------------------------
DSP Block #:              1 2 3 4 5
# of MULT36X36B                    
# of MULT18X18B                    
# of MULT18X18MACB                 
# of MULT18X18ADDSUBB              
# of MULT18X18ADDSUBSUMB           
# of MULT9X9B                      
# of MULT9X9ADDSUBB                
# of MULT9X9ADDSUBSUMB             

Total placer CPU time: 28 secs 

Dumping design to file tag_mem.dir/5_1.ncd.

1 potential circuit loop found in timing analysis.
0 connections routed; 269 unrouted.
Starting router resource preassignment
Completed router resource preassignment. Real time: 42 secs 

Congestion Driven Router (CDR) is turned on.
CDR effort level is set at 0.
To turn CDR off, please set "-exp parCDR=0" on command line.

Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
269 successful; 0 unrouted; (0) real time: 42 secs 
Dumping design to file tag_mem.dir/5_1.ncd.
Total CPU time 39 secs 
Total REAL time: 42 secs 
Completely routed.
End of route.  269 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.
Timing score: 0 

Total REAL time to completion: 43 secs 


All signals are completely routed.


par done!

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