adi_ssl_init.c

The files adi_ssl_init.h and adi_ssl_init.c are used to define the functions adi_ssl_Init()

/*********************************************************************************

Copyright(c) 2005 Analog Devices, Inc. All Rights Reserved. 

This software is proprietary and confidential.  By using this software you agree
to the terms of the associated Analog Devices License Agreement.  


$RCSfile: adi_ssl_Init.c,v $
$Revision: 1.38 $
			
*********************************************************************************/

/*********************************************************************

This file contains a convenient mechanism to initialize and terminate 
all system services and the device manager.  The application should 
modify the sizings located in the adi_ssl_Init.h file as needed by their
application, then add this file to their list of source files for
their project.  

The application should then make one call to the function adi_ssl_Init(), 
insuring the return value from the function call returns the value 0.  
This function call initialized all services and the device manager 
according to the sizings defined in adi_ssl_init.h.

When no longer needed, the application can then one call to the function
adi_ssl_Terminate(), insuring the return value from the function call
returns the value 0.  This function call terminates all services and 
the device manager.  

The handles to the DMA and Device Manager are stored in the global 
variables adi_dma_ManagerHandle and adi_dev_ManagerHandle, respectively.
These handles can be passed to subsequent adi_dev_Open() calls as
necessary.

DO NOT MODIFY ANYTHING IN THIS FILE

*********************************************************************/


/*********************************************************************

Include files

*********************************************************************/

#include <services/services.h>		// system service includes
#include <drivers/adi_dev.h>        // device driver includes

#include "adi_ssl_init.h"           // initialization sizings



/*********************************************************************

Handles

This section provides storage for handles into the services and device 
manager.  The application may use these handles into calls such as
adi_dev_Open() for opening device drivers, adi_dma_OpenChannel() for
opening DMA channels etc.  


*********************************************************************/

ADI_DMA_MANAGER_HANDLE adi_dma_ManagerHandle;   // handle to the DMA manager
ADI_DEV_MANAGER_HANDLE adi_dev_ManagerHandle;   // handle to the device manager
	

/*********************************************************************

Global storage data

This section provides memory, based on the sizing defined above, for 
each of the services. 

*********************************************************************/

static  u8  InterruptServiceData        [ADI_INT_SECONDARY_MEMORY * ADI_SSL_INT_NUM_SECONDARY_HANDLERS];
static  u8  DeferredCallbackServiceData [ADI_DCB_QUEUE_SIZE * ADI_SSL_DCB_NUM_SERVERS];
static  u8  DMAServiceData              [ADI_DMA_BASE_MEMORY + (ADI_DMA_CHANNEL_MEMORY *  ADI_SSL_DMA_NUM_CHANNELS)];
static  u8  FlagServiceData             [ADI_FLAG_CALLBACK_MEMORY *  ADI_SSL_FLAG_NUM_CALLBACKS];
static  u8  SemaphoreServiceData        [ADI_SEM_SEMAPHORE_MEMORY *  ADI_SSL_SEM_NUM_SEMAPHORES];

static  u8  DevMgrData                  [ADI_DEV_BASE_MEMORY + (ADI_DEV_DEVICE_MEMORY * ADI_SSL_DEV_NUM_DEVICES)];



/*********************************************************************

	Function:		adi_ssl_Init

	Description:	Initializes the system services and device manager.


*********************************************************************/

u32 adi_ssl_Init(void) {
    
    u32 i;
    u32 Result;


	/* definitions for asynch memory controller commands */

	/*  global control register fields */
	/*  clkout enable */
	ADI_EBIU_ASYNCH_CLKOUT clkout_enable = ADI_EBIU_ASYNCH_CLKOUT_ENABLE;
	/*  which banks to enable */
	ADI_EBIU_ASYNCH_BANK_ENABLE banks_enable = ADI_EBIU_ASYNCH_BANK0_1_2_3;
 
	/* bank timing parameters - specified in cycles */
	/* transition times for the four banks */
	ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_trans_time = {ADI_EBIU_BANK_ALL, { ADI_EBIU_ASYNCH_TT_4_CYCLES, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };
 
	/* time between Read Enable assertion to de-assertion */
	ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_read_access_time = { ADI_EBIU_BANK_ALL,  { 0xB, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };
 
	/* time between Write Enable  assertion to de-assertion */
	ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_write_access_time = { ADI_EBIU_BANK_ALL,  { 7, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };
  
	/* time from beginning of memory cycle to R/W-enable */
	ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_setup_time = { ADI_EBIU_BANK_ALL,  { ADI_EBIU_ASYNCH_ST_3_CYCLES, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };
   
	/* time from de-assertion  to end of memory cycle */
	ADI_EBIU_ASYNCH_BANK_TIMING asynch_bank_hold_time = {ADI_EBIU_BANK_ALL,  { ADI_EBIU_ASYNCH_HT_2_CYCLES, { 0, ADI_EBIU_TIMING_UNIT_NANOSEC } } };

	/* specify whether ARDY enabled (is used to insert extra wait states) */
	ADI_EBIU_ASYNCH_BANK_VALUE asynch_bank_ardy_enable = { ADI_EBIU_BANK_ALL, { ardy_enable: ADI_EBIU_ASYNCH_ARDY_DISABLE } };

    	
	/* specify whether ARDY is sampled low or high */	
	ADI_EBIU_ASYNCH_BANK_VALUE asynch_bank_ardy_polarity = { ADI_EBIU_BANK_ALL, { ardy_polarity: ADI_EBIU_ASYNCH_ARDY_POLARITY_LOW } };



/********************************************************************/
#if defined(__ADSP_EDINBURGH__)		// BF533 EZKit

	ADI_PWR_COMMAND_PAIR ezkit_power[] = { 

#if defined ADI_SSL_BF533_6V 
    	{ ADI_PWR_CMD_SET_PROC_VARIANT,(void*)ADI_PWR_PROC_BF533SKBC600_6V  },  // 600Mhz ADSP-BF533 6V variant 
#else
    	{ ADI_PWR_CMD_SET_PROC_VARIANT,(void*)ADI_PWR_PROC_BF533SKBC600  },     // 600Mhz ADSP-BF533 variant 
#endif
    	{ ADI_PWR_CMD_SET_PACKAGE,     (void*)ADI_PWR_PACKAGE_MBGA       },     // in MBGA packaging, as on all EZ-KITS
    	{ ADI_PWR_CMD_SET_VDDEXT,      (void*)ADI_PWR_VDDEXT_330         },     // external voltage supplied to the voltage regulator is 3.3V

#if defined ADI_SSL_EXT_VOLTAGE_REG
	{ ADI_PWR_CMD_SET_VDDINT,      (void*)ADI_SSL_EXT_VDDINT         },	/* Externally supplied VDDINT (see adi_ssl_Init.h)*/		
#endif

    	{ ADI_PWR_CMD_SET_CLKIN,       (void*)27                         },	// the CLKIN frequency 27 MHz
    	{ ADI_PWR_CMD_END,             0                                 } 
	}; 

	ADI_EBIU_TIMING_VALUE     twrmin       = {1,{7500, ADI_EBIU_TIMING_UNIT_PICOSEC}};   // set min TWR to 1 SCLK cycle + 7.5ns	
	ADI_EBIU_TIMING_VALUE     refresh      = {8192,{64, ADI_EBIU_TIMING_UNIT_MILLISEC}}; // set refresh period to 8192 cycles in 64ms
	ADI_EBIU_TIME             trasmin      = {44, ADI_EBIU_TIMING_UNIT_NANOSEC};         // set min TRAS to 44ns
	ADI_EBIU_TIME             trpmin       = {20, ADI_EBIU_TIMING_UNIT_NANOSEC};	     // set min TRP to 20ns
	ADI_EBIU_TIME             trcdmin      = {20, ADI_EBIU_TIMING_UNIT_NANOSEC}; 	     // set min TRCD to 20ns
	u32                       cl_threshold = 100;                                        // set cl threshold to 100 Mhz
#if defined( ADI_SSL_EDIN_REV_1_7 )
	ADI_EBIU_SDRAM_BANK_VALUE bank_size    = {0, {size: ADI_EBIU_SDRAM_BANK_64MB }};      // set bank size to 64MB
	ADI_EBIU_SDRAM_BANK_VALUE bank_width   = {0, {width: ADI_EBIU_SDRAM_BANK_COL_10BIT}}; // set column address width to 10-Bit
#else
	ADI_EBIU_SDRAM_BANK_VALUE bank_size    = {0, {size: ADI_EBIU_SDRAM_BANK_32MB }};     // set bank size to 64MB
	ADI_EBIU_SDRAM_BANK_VALUE bank_width   = {0, {width: ADI_EBIU_SDRAM_BANK_COL_9BIT}}; // set column address width to 9-Bit
#endif

	ADI_EBIU_COMMAND_PAIR ezkit_ram[] = { 
	{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE,     (void*)&bank_size   },
       	{ ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank_width  },
       	{ ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD,  (void*)cl_threshold },
      	{ ADI_EBIU_CMD_SET_SDRAM_TRASMIN,       (void*)&trasmin     }, 
       	{ ADI_EBIU_CMD_SET_SDRAM_TRPMIN,        (void*)&trpmin      }, 
       	{ ADI_EBIU_CMD_SET_SDRAM_TRCDMIN,       (void*)&trcdmin     }, 
       	{ ADI_EBIU_CMD_SET_SDRAM_TWRMIN,        (void*)&twrmin      },
       	{ ADI_EBIU_CMD_SET_SDRAM_REFRESH,       (void*)&refresh     },
       	/* Asynch Commands memory controller commands */ 
       	{ ADI_EBIU_CMD_SET_ASYNCH_CLKOUT_ENABLE,          (void*)&clkout_enable },
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ENABLE,            (void*)&banks_enable },                                 
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_TRANSITION_TIME,   (void*)&asynch_bank_trans_time  },
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_ACCESS_TIME,  (void*)&asynch_bank_read_access_time  }, 
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_ACCESS_TIME, (void*)&asynch_bank_write_access_time  },
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_SETUP_TIME,        (void*)&asynch_bank_setup_time  }, 
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_HOLD_TIME,         (void*)&asynch_bank_hold_time  },
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_ENABLE,       (void*)&asynch_bank_ardy_enable  },  
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_POLARITY,     (void*)&asynch_bank_ardy_polarity },  
      	{ ADI_EBIU_CMD_END,                     0                   }
	};
	
#endif
/********************************************************************/
#if defined(__ADSP_BRAEMAR__)		// BF537 EZKit

	ADI_PWR_COMMAND_PAIR ezkit_power[] = { 
    	{ ADI_PWR_CMD_SET_PROC_VARIANT,(void*)ADI_PWR_PROC_BF537SKBC1600 }, // 600Mhz ADSP-BF537
    	{ ADI_PWR_CMD_SET_PACKAGE,     (void*)ADI_PWR_PACKAGE_MBGA       }, // in MBGA packaging, as on all EZ-KITS
    	{ ADI_PWR_CMD_SET_VDDEXT,      (void*)ADI_PWR_VDDEXT_330         }, // external voltage supplied to the voltage regulator is 3.3V
#if defined ADI_SSL_EXT_VOLTAGE_REG
	{ ADI_PWR_CMD_SET_VDDINT,      (void*)ADI_SSL_EXT_VDDINT         },	/* Externally supplied VDDINT (see adi_ssl_Init.h)*/		
#endif
    	{ ADI_PWR_CMD_SET_CLKIN,       (void*)25                         },	// the CLKIN frequency 25 MHz
    	{ ADI_PWR_CMD_END,             0                                 } 
	}; 

	ADI_EBIU_TIMING_VALUE     twrmin       = {1,{7500, ADI_EBIU_TIMING_UNIT_PICOSEC}};    // set min TWR to 1 SCLK cycle + 7.5ns	
	ADI_EBIU_TIMING_VALUE     refresh      = {8192,{64, ADI_EBIU_TIMING_UNIT_MILLISEC}};  // set refresh period to 8192 cycles in 64ms
	ADI_EBIU_TIME             trasmin      = {44, ADI_EBIU_TIMING_UNIT_NANOSEC};          // set min TRAS to 44ns
	ADI_EBIU_TIME             trpmin       = {20, ADI_EBIU_TIMING_UNIT_NANOSEC};	      // set min TRP to 20ns
	ADI_EBIU_TIME             trcdmin      = {20, ADI_EBIU_TIMING_UNIT_NANOSEC}; 	      // set min TRCD to 20ns
	u32                       cl_threshold = 100;                                         // set cl threshold to 100 Mhz
	ADI_EBIU_SDRAM_BANK_VALUE bank_size    = {0, {size: ADI_EBIU_SDRAM_BANK_64MB }};      // set bank size to 64MB
	ADI_EBIU_SDRAM_BANK_VALUE bank_width   = {0, {width: ADI_EBIU_SDRAM_BANK_COL_10BIT}}; // set column address width to 10-Bit

	ADI_EBIU_COMMAND_PAIR ezkit_ram[] = { 
		{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE,     (void*)&bank_size   },
       	{ ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank_width  },
       	{ ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD,  (void*)cl_threshold },
      	{ ADI_EBIU_CMD_SET_SDRAM_TRASMIN,       (void*)&trasmin     }, 
       	{ ADI_EBIU_CMD_SET_SDRAM_TRPMIN,        (void*)&trpmin      }, 
       	{ ADI_EBIU_CMD_SET_SDRAM_TRCDMIN,       (void*)&trcdmin     }, 
       	{ ADI_EBIU_CMD_SET_SDRAM_TWRMIN,        (void*)&twrmin      },
       	{ ADI_EBIU_CMD_SET_SDRAM_REFRESH,       (void*)&refresh     },
       	/* Asynch Commands memory controller commands */ 
       	{ ADI_EBIU_CMD_SET_ASYNCH_CLKOUT_ENABLE,          (void*)&clkout_enable },
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ENABLE,            (void*)&banks_enable },                                 
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_TRANSITION_TIME,   (void*)&asynch_bank_trans_time  },
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_READ_ACCESS_TIME,  (void*)&asynch_bank_read_access_time  }, 
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_WRITE_ACCESS_TIME, (void*)&asynch_bank_write_access_time  },
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_SETUP_TIME,        (void*)&asynch_bank_setup_time  }, 
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_HOLD_TIME,         (void*)&asynch_bank_hold_time  },
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_ENABLE,       (void*)&asynch_bank_ardy_enable  },  
       	{ ADI_EBIU_CMD_SET_ASYNCH_BANK_ARDY_POLARITY,     (void*)&asynch_bank_ardy_polarity },  
      	{ ADI_EBIU_CMD_END,                     0                   }
	};
	
#endif
/********************************************************************/
#if defined(__ADSP_TETON__)		// BF561 EZKit
	ADI_PWR_COMMAND_PAIR ezkit_power[] = { 
    	{ ADI_PWR_CMD_SET_PROC_VARIANT,         (void*)ADI_PWR_PROC_BF561SKBCZ500X  },  // 500Mhz ADSP-BF561
    	{ ADI_PWR_CMD_SET_PACKAGE,              (void*)ADI_PWR_PACKAGE_MBGA         },  // in MBGA packaging, as on all EZ-KITS
    	{ ADI_PWR_CMD_SET_VDDEXT,               (void*)ADI_PWR_VDDEXT_330           },  // external voltage supplied to the voltage regulator is 3.3V
#if defined ADI_SSL_EXT_VOLTAGE_REG
	{ ADI_PWR_CMD_SET_VDDINT,      (void*)ADI_SSL_EXT_VDDINT         },	/* Externally supplied VDDINT (see adi_ssl_Init.h)*/		
#endif
    	{ ADI_PWR_CMD_SET_CLKIN,                (void*)30                           },	// the CLKIN frequency 30 MHz

#if defined( ADI_SSL_DUAL_CORE )
    	{ ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED,    NULL                                },	// enable autosync so the core A and B sync up