i2c_isr.s43

I2c details for MSP430

            DW      SCL_R1LH                ; Bit 1 (first clk rising edge)
            DW      SCL_R2to8HL             ; Bit 2 (2nd clk falling edge)
            DW      SCL_R2to8HL             ; Bit 3 (3rd clk falling edge)
            DW      SCL_R2to8HL             ; Bit 4 (4th clk falling edge)
            DW      SCL_R2to8HL             ; Bit 5 (5th clk falling edge)
            DW      SCL_R2to8HL             ; Bit 6 (6th clk falling edge)
            DW      SCL_R2to8HL             ; Bit 7 (7th clk falling edge)
            DW      SCL_R2to8HL             ; Bit 8 (8th clk falling edge)
            DW      SCL_R9HL                ; Free SDA (9th clk falling edge)
            DW      SCL_R9LH                ; Check ACK (9th clk rising edge)
                                            ; Re-init R4



;-------------------------------------------------------------------------------
SCL_W1LH    ;This ISR handles the 1st bit clocked in on the rising edge of SCL
;-------------------------------------------------------------------------------
            bis.b   #SCL,&P1IES             ; Set falling edge for SCL
            bit.b   #SDA,&P2IN              ; Check SDA and store in Carry Reg.
            bic.b   #SCL,&P1IFG             ; Reset SCL interrupt flag
            bic.b   #SDA,&P2IFG             ; Clear flag, FOR STP_CON DETECT
            bis.b   #SDA,&P2IE              ; Enable SDA INT
            rlc.b   IICDATA                 ; Shift SDA bit into the buffer
            reti


;-------------------------------------------------------------------------------
SCL_W1HL    ;This ISR is called on the falling edge of the first SCL clock
;-------------------------------------------------------------------------------
            bic.b   #SCL,&P1IES             ; Set rising edge for SCL
            bic.b   #SCL,&P1IFG             ; Reset interrupt flag
            bic.b   #SDA,&P2IE              ; 1st FALLING SCL TO disable SDA INT
            reti


;-------------------------------------------------------------------------------
SCL_W2to6LH ;This ISR handles the 2nd through 6th bits on rising SCL edge
;-------------------------------------------------------------------------------
            bic.b   #SCL,&P1IFG             ; Reset interrupt flag
            bit.b   #SDA,&P2IN              ; Check SDA and store in Carry Reg.
            rlc.b   IICDATA                 ; Shift SDA bit into the buffer
            reti


;-------------------------------------------------------------------------------
SCL_W7LH    ;This ISR is called on the rising edge of the 7th SCL clock
;-------------------------------------------------------------------------------
            bic.b   #SCL,&P1IFG             ; Reset interrupt flag
            bit.b   #SDA,&P2IN              ; Check SDA and store in Carry Reg.
            rlc.b   IICDATA                 ; Shift SDA bit into the buffer

            cmp     #W_ACK,BR_ADD           ; Check if BR_ADD is modified
            jz      WRT_7                   ; If Yes, Jump to write-in branch

            cmp.b   #IICOA,IICDATA          ; If not, check if it is own addr
            jnz     NACK_T                  ; If not, Jump to NACK_T
            mov     #RW_BIT,BR_CLK_8        ; Set branch to check R/W bit
            reti

WRT_7       mov     #WRITE_IN,BR_CLK_8      ; Set BR_CLK_8 to write-in branch
            reti


;-------------------------------------------------------------------------------
SCL_W8LH    ;This ISR handles the 8th bit and sets up for ACK on falling SCL
;-------------------------------------------------------------------------------
            bis.b   #SCL,&P1IES             ; Set falling edge for SCL.
            bit.b   #SDA,&P2IN              ; Check SDA and store in Carry Reg.
            bic.b   #SCL,&P1IFG             ; Reset interrupt flag

            br      BR_CLK_8                ; R/W bit or write-in Branching

RW_BIT      jc      READ_CMD
WRITE_CMD   mov     #W_ACK,BR_ADD           ; Set BR_ADD to write-ACK branch
            reti
READ_CMD    mov     #R_ACK,BR_ADD           ; Set BR_ADD to Read-Ack branch
            reti

WRITE_IN    rlc.b   IICDATA                 ; Shift SDA bit into the buffer
            reti


;-------------------------------------------------------------------------------
SCL_W8HL    ;This ISR output ACK and setting for write or read process
            ;on falling edge of 8th bit
;-------------------------------------------------------------------------------
            bis.b   #SDA,&P2DIR             ; Output "0" for SDA
            bic.b   #SCL,&P1IFG             ; Reset SCL interrupt flag

            br      BR_ADD

W_ACK       mov.b   IICDATA,RAM(R5)         ; Store the received data into RAM
            inc.b   R5                      ; RAM pointer increase 1
            and.b   #0FH,R5                 ; Limit the RAM buffer size to 16
            reti

R_ACK       mov.b   IICDATA,RAM             ; Store the Addr into RAM
            inc.b   R5                      ; RAM pointer increase 1
            mov.b   RAM(R5),IICDATA         ; Move out one byte from RAM buffer
            mov     #SCL_READ,R4            ; Set to Read-out ISRs
            reti

NACK_T      jmp      IIC_STP2               ; JMP TO STOP COND. SETING


;-------------------------------------------------------------------------------
SCL_W9HL    ;This ISR release SDA and reset the routine address pointer
            ;on falling edge of 9th clock
;-------------------------------------------------------------------------------
            bic.b   #SDA,&P2DIR             ; Release SDA
            bic.b   #SCL,&P1IES             ; Set rising edge for SCL
            bic.b   #SCL,&P1IFG             ; Reset interrupt flag
            mov     #SCL_WRT,R4             ; Re-init the Write-in ISRs pointer
            reti


;-------------------------------------------------------------------------------
SCL_R1LH    ;This ISR detect the stop_con in read-out routine
;-------------------------------------------------------------------------------
            bis.b   #SCL,&P1IES             ; Set falling edge for SCL
            bic.b   #SCL,&P1IFG             ; Clear SCL INT flag
            bic.b   #SDA,&P2IFG             ; Clear SDA INT Flag
            bis.b   #SDA,&P2IE              ; Enable SDA INT for STOP CON
            reti


;-------------------------------------------------------------------------------
;These ISRs output a "1" or "0" bit by bit on every falling edge
;-------------------------------------------------------------------------------
SCL_R1HL    bic.b   #SCL,&P1IES             ; Set rising edge SCL for SCL_R1LH
SCL_R2to8HL rlc.b   IICDATA                 ; Shift out one bit
            jc      SET_1                   ; Check 1 or 0
SET_0       bis.b   #SDA,&P2DIR             ; SDA = 0
            jmp     SET_OK
SET_1       bic.b   #SDA,&P2DIR             ; SDA = 1
SET_OK      bic.b   #SCL,&P1IFG             ; Clear SCL INT flag
            bic.b   #SDA,&P2IE              ; Disable SDA INT, NO STP CON
            reti


;-------------------------------------------------------------------------------
SCL_R9HL    ;This ISR release SDA for receiving ACK from master unit
;-------------------------------------------------------------------------------
            bic.b   #SDA,&P2DIR             ; Release SDA
            bic.b   #SCL,&P1IES             ; Set Rising edge of SCL
            bic.b   #SCL,&P1IFG             ; Clear SCL INT flag
            reti


;-------------------------------------------------------------------------------
SCL_R9LH    ;This ISR receive ACK or NACK
;-------------------------------------------------------------------------------
            bit.b   #SDA,&P2IN              ; Check SDA and store in Carry Reg.
            jnc     ACK_READ                ; If "0", Jump to ACK_READ

NACK_READ   bic.b   #SCL,&P1IES             ; Set rising edge of SCL
            bic.b   #SCL,&P1IFG             ; Clear SCL INT flag
            mov     #SCL_WRT,R4             ; Set ISR pointer to write-in ISRs
            mov     #NACK_T,BR_ADD          ; Pre-set ACK branching to NACK_T
            reti

ACK_READ    bis.b   #SCL,&P1IES             ; Set falling edge of SCL
            bic.b   #SCL,&P1IFG             ; Clear SCL INT flag
            mov     #SCL_READ,R4            ; Set ISR pointer to read-out ISRs
            inc.b   R5                      ; RAM pointer increase 1
            and.b   #0FH,R5                 ; Limit the RAM buffer size to 16
            mov.b   RAM(R5),IICDATA         ; Move out next byte from RAM buffer
            reti


;-------------------------------------------------------------------------------
; Interrupt Vector
;-------------------------------------------------------------------------------
            COMMON  INTVEC
;-------------------------------------------------------------------------------
            ORG     PORT1_VECTOR
            DW      ISR_SCL

            ORG     PORT2_VECTOR
            DW      ISR_SDA

END