i2c_isr.s43

I2c details for MSP430

#include <msp430x11x1.h>

;-------------------------------------------------------------------------------
; Name: i2c_isr.s43
; Func: I2C firmware module
; Ver.: 1.1
; Date: June-2005
; Auth: Thomas Kot
;       MSP430
;       Texas Instruments Inc.
; Rem.: Build with IAR EW V4.3A
;-------------------------------------------------------------------------------
; Exported Symbols
;-------------------------------------------------------------------------------
            PUBLIC  INIT_IIC
            PUBLIC  IIC_STP2
            PUBLIC  RAM
            PUBLIC  SCL
            PUBLIC  SDA


;-------------------------------------------------------------------------------
; Define Constant
;-------------------------------------------------------------------------------
SCL         EQU     01H                     ; P1.0 is used for SCL
SDA         EQU     01H                     ; P2.0 is used for SDA
IICOA       EQU     62H                     ; I2C own Address



;-------------------------------------------------------------------------------
; Define RAM
;-------------------------------------------------------------------------------
            RSEG    DATA16_N
;-------------------------------------------------------------------------------
RAM         DS      16
IICDATA     DS      1


;-------------------------------------------------------------------------------
            RSEG    DATA16_N
;-------------------------------------------------------------------------------
            EVEN
BR_ADD      DW      1
BR_CLK_8    DW      1


;-------------------------------------------------------------------------------
; Implementation
;-------------------------------------------------------------------------------
            RSEG    CODE
;-------------------------------------------------------------------------------
INIT_IIC    call    #MAIN_ASM
            ret

MAIN_ASM
            mov.b   #10H,R5
CLEAR_RAM   dec     R5
            mov.b   #01h,RAM(R5)
            jnz     CLEAR_RAM

            call    #INIT_SGL               ; Init signal pin
            call    #INIT_PORT              ; Init I/O port
            call    #INIT_REG               ; Init Register
            ret


;-------------------------------------------------------------------------------
INIT_SGL    ; Init Data ready signal
;-------------------------------------------------------------------------------
            bic.b   #02H,&P1OUT             ; Data ready signal, Normal Low
            bis.b   #02H,&P1DIR             ; Interrupt signal to main chip
            ret


;-------------------------------------------------------------------------------
INIT_REG    ; R4 - Branch pointer
            ; R5 - Ram index
            ; IICDATA - Store a Byte for I2C transmission
;-------------------------------------------------------------------------------
            mov.b   #00H,IICDATA
            mov     #SCL_WRT,R4
            mov     #0000H,R5
            ret


;-------------------------------------------------------------------------------
INIT_PORT   ; Set SCL and SDA to inputs
            ; SDA interrupts on high-to-low transition
            ; SCL interrupts on low-to-high transition
            ; initially, just SDA interrupt is set
;-------------------------------------------------------------------------------
            bic.b   #SDA,&P2OUT             ; When the pins are set to
            bic.b   #SCL,&P1OUT             ; output, low level should be seen
            bic.b   #SCL,&P1DIR             ; SCL and SDA defined as inputs
INIT_INT    bic.b   #SDA,&P2DIR
            bis.b   #SDA,&P2IES             ; INT. on high-to-low transition
            bic.b   #SCL,&P1IES             ; INT. on low-to-high transition
            bic.b   #SCL,&P1IE              ; Disable SCL interrupt
            bis.b   #SDA,&P2IE              ; Enable SDA interrupt
            bic.b   #SCL,&P1IFG             ; Reset interrupt flag
            bic.b   #SDA,&P2IFG
            ret


;-------------------------------------------------------------------------------
ISR_SDA     ; Port 2 ISR, check Start or Stop condition from P2.0 and P1.0
            ; Or it can check I/O interrupt from P2.1 to P2.7
;-------------------------------------------------------------------------------
            bit.b   #SCL,&P1IN              ; Test SCL High
            jnc     NOT_SDA
            bit.b   #SDA,&P2IFG             ; Test SDA interrupt

NOT_SDA     mov.b   #00H,&P2IFG             ; CLR P2IFG
            jc      IIC_SP                  ; Jump to I2C start/stop routine
            ;
            ;                               ; These few lines are left blank.
            ;                               ; User can add Instructions here
            ;                               ; for I/O INT. from P2.1 to P2.7
            ;                               ; used for Key Matrix Scanning
            ;
            reti


;-------------------------------------------------------------------------------
IIC_SP      ; I2C Start/Stop sorter
;-------------------------------------------------------------------------------
            bit.b   #SDA,&P2IES             ; Test START / STOP Condition
            jc      IIC_START


;-------------------------------------------------------------------------------
IIC_STOP    ; Handles stop condition caused by SDA interrupt or error
;-------------------------------------------------------------------------------
            bic.b   #02H,&P1OUT             ; Reset IR_DATA READY Pin P1.1
IIC_STP2    bis     #CCIE, &TACCTL1         ; Enable for IR data capture

            mov     #TASSEL_2+ID_3+TACLR+TAIE,&TACTL
                                            ; SMCLK, DIV BY 8, STOP MODE,
                                            ; INT ENABLE, FLAG CLEAR

            mov     #SCL_WRT,R4             ; Init the SCL routine addr pointer
            call    #INIT_PORT              ; Init port setting for SCL and SDA
            reti


;-------------------------------------------------------------------------------
IIC_START   ; Handles a start condition caused by SDA interrupt
;-------------------------------------------------------------------------------
            bic.b   #SCL,&P1IFG             ; P1.0 clear INT flag
            bis.b   #SCL,&P1IE              ; P1.0 INT enable for SCL
            bic.b   #SDA,&P2IES             ; P2.0 set to rising edge for SDA
            bic.b   #SDA,&P2IFG             ; P2.0 clear INT flag
            bic.b   #SDA,&P2IE              ; P2.0 INT disable for SDA
            mov.b   #00H,IICDATA            ; Reset IICDATA for addr detect
            mov     #NACK_T,BR_ADD          ; Pre-set ACK branching to NACK_T
            bis     #MC_2, &TACTL           ; Start Timer
            bic     #CCIE, &TACCTL1         ; Disabe IR capture
            mov     #SCL_WRT,R4             ; Pre-set SCL branching pointer
            mov     #0000H,R5               ; Reset RAM index pointer
            reti


;-------------------------------------------------------------------------------
ISR_SCL     ; ISR for SCL interrupts
;-------------------------------------------------------------------------------
            br      @R4+
SCL_WRT                                     ; Addres detect and Write in ISRs
            DW      SCL_W1LH                ; Bit 1 (first clk rising edge)
            DW      SCL_W1HL                ; Bit 1 (first clk falling edge)
            DW      SCL_W2to6LH             ; Bit 2 (2nd  clk rising edge)
            DW      SCL_W2to6LH             ; Bit 3 (3rd  clk rising edge)
            DW      SCL_W2to6LH             ; Bit 4 (4th  clk rising edge)
            DW      SCL_W2to6LH             ; Bit 5 (5th  clk rising edge)
            DW      SCL_W2to6LH             ; Bit 6 (6th  clk rising edge)
            DW      SCL_W7LH                ; Bit 7 (7th  clk rising edge)
            DW      SCL_W8LH                ; Bit 8 (8th  clk rising edge)
            DW      SCL_W8HL                ; Set ACK (8th  clk falling edge)
            DW      SCL_W9HL                ; Re-init R4 (9th  clk falling edge)


SCL_READ                                    ; Read out ISRs
            DW      SCL_R1HL                ; Bit 1 (first clk falling edge)