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📄 cslr_h3a_001.h

📁 TI的DM6446的硬件平台搭建的相关例子
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#ifndef _CSLR_H3A_1_H_
#define _CSLR_H3A_1_H_
/*********************************************************************
 * Copyright (C) 2003-2004 Texas Instruments Incorporated. 
 * All Rights Reserved 
 *********************************************************************/
 /** \file cslr_h3a_1.h
 * 
 * \brief This file contains the Register Desciptions for H3A
 * 
 *********************************************************************/

#include <cslr.h>

#include <tistdtypes.h>

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    volatile Uint32 PID;
    volatile Uint32 PCR;
    volatile Uint32 AFPAX1;
    volatile Uint32 AFPAX2;
    volatile Uint32 AFPAXSTART;
    volatile Uint32 AFIIRSH;
    volatile Uint32 AFBUFST;
    volatile Uint32 AFCOEF010;
    volatile Uint32 AFCOEF032;
    volatile Uint32 AFCOEFF054;
    volatile Uint32 AFCOEFF076;
    volatile Uint32 AFCOEFF098;
    volatile Uint32 AFCOEFF0010;
    volatile Uint32 AFCOEF110;
    volatile Uint32 AFCOEF132;
    volatile Uint32 AFCOEFF154;
    volatile Uint32 AFCOEFF176;
    volatile Uint32 AFCOEFF198;
    volatile Uint32 AFCOEFF1010;
    volatile Uint32 AEWWIN1;
    volatile Uint32 AEWINSTART;
    volatile Uint32 AEWINBLK;
    volatile Uint32 AEWSUBWIN;
    volatile Uint32 AEWBUFST;
} CSL_H3aRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* PID */

#define CSL_H3A_PID_TID_MASK             (0x00FF0000u)
#define CSL_H3A_PID_TID_SHIFT            (0x00000010u)
#define CSL_H3A_PID_TID_RESETVAL         (0x00000008u)

#define CSL_H3A_PID_CID_MASK             (0x0000FF00u)
#define CSL_H3A_PID_CID_SHIFT            (0x00000008u)
#define CSL_H3A_PID_CID_RESETVAL         (0x000000FEu)

#define CSL_H3A_PID_PREV_MASK            (0x000000FFu)
#define CSL_H3A_PID_PREV_SHIFT           (0x00000000u)
#define CSL_H3A_PID_PREV_RESETVAL        (0x00000000u)

#define CSL_H3A_PID_RESETVAL             (0x0008FE00u)

/* PCR */

#define CSL_H3A_PCR_AVE2LMT_MASK         (0xFFC00000u)
#define CSL_H3A_PCR_AVE2LMT_SHIFT        (0x00000016u)
#define CSL_H3A_PCR_AVE2LMT_RESETVAL     (0x000003FFu)

#define CSL_H3A_PCR_BUSYAEAWB_MASK       (0x00040000u)
#define CSL_H3A_PCR_BUSYAEAWB_SHIFT      (0x00000012u)
#define CSL_H3A_PCR_BUSYAEAWB_RESETVAL   (0x00000000u)

#define CSL_H3A_PCR_AEW_ALAW_EN_MASK     (0x00020000u)
#define CSL_H3A_PCR_AEW_ALAW_EN_SHIFT    (0x00000011u)
#define CSL_H3A_PCR_AEW_ALAW_EN_RESETVAL (0x00000000u)

/*----AEW_ALAW_EN Tokens----*/
#define CSL_H3A_PCR_AEW_ALAW_EN_DISABLE  (0x00000000u)
#define CSL_H3A_PCR_AEW_ALAW_EN_ENABLE   (0x00000001u)

#define CSL_H3A_PCR_AEW_EN_MASK          (0x00010000u)
#define CSL_H3A_PCR_AEW_EN_SHIFT         (0x00000010u)
#define CSL_H3A_PCR_AEW_EN_RESETVAL      (0x00000000u)

/*----AEW_EN Tokens----*/
#define CSL_H3A_PCR_AEW_EN_DISABLE       (0x00000000u)
#define CSL_H3A_PCR_AEW_EN_ENABLE        (0x00000001u)

#define CSL_H3A_PCR_BUSYAF_MASK          (0x00008000u)
#define CSL_H3A_PCR_BUSYAF_SHIFT         (0x0000000Fu)
#define CSL_H3A_PCR_BUSYAF_RESETVAL      (0x00000000u)

#define CSL_H3A_PCR_FVMODE_MASK          (0x00004000u)
#define CSL_H3A_PCR_FVMODE_SHIFT         (0x0000000Eu)
#define CSL_H3A_PCR_FVMODE_RESETVAL      (0x00000000u)

/*----FVMODE Tokens----*/
#define CSL_H3A_PCR_FVMODE_SUMMODE       (0x00000000u)
#define CSL_H3A_PCR_FVMODE_PEAKMODE      (0x00000001u)

#define CSL_H3A_PCR_RGBPOS_MASK          (0x00003800u)
#define CSL_H3A_PCR_RGBPOS_SHIFT         (0x0000000Bu)
#define CSL_H3A_PCR_RGBPOS_RESETVAL      (0x00000000u)

/*----RGBPOS Tokens----*/
#define CSL_H3A_PCR_RGBPOS_GR_GB_BAYER   (0x00000000u)
#define CSL_H3A_PCR_RGBPOS_RG_GB_BAYER   (0x00000001u)
#define CSL_H3A_PCR_RGBPOS_GR_BG_BAYER   (0x00000002u)
#define CSL_H3A_PCR_RGBPOS_RG_BG_BAYER   (0x00000003u)
#define CSL_H3A_PCR_RGBPOS_GG_RB_CUSTOM  (0x00000004u)
#define CSL_H3A_PCR_RGBPOS_RB_GG_CUSTOM  (0x00000005u)

#define CSL_H3A_PCR_MED_TH_MASK          (0x000007F8u)
#define CSL_H3A_PCR_MED_TH_SHIFT         (0x00000003u)
#define CSL_H3A_PCR_MED_TH_RESETVAL      (0x000000FFu)

#define CSL_H3A_PCR_AF_MED_EN_MASK       (0x00000004u)
#define CSL_H3A_PCR_AF_MED_EN_SHIFT      (0x00000002u)
#define CSL_H3A_PCR_AF_MED_EN_RESETVAL   (0x00000000u)

/*----AF_MED_EN Tokens----*/
#define CSL_H3A_PCR_AF_MED_EN_DISABLE    (0x00000000u)
#define CSL_H3A_PCR_AF_MED_EN_ENABLE     (0x00000001u)

#define CSL_H3A_PCR_AF_ALAW_EN_MASK      (0x00000002u)
#define CSL_H3A_PCR_AF_ALAW_EN_SHIFT     (0x00000001u)
#define CSL_H3A_PCR_AF_ALAW_EN_RESETVAL  (0x00000000u)

/*----AF_ALAW_EN Tokens----*/
#define CSL_H3A_PCR_AF_ALAW_EN_DISABLE   (0x00000000u)
#define CSL_H3A_PCR_AF_ALAW_EN_ENABLE    (0x00000001u)

#define CSL_H3A_PCR_AF_EN_MASK           (0x00000001u)
#define CSL_H3A_PCR_AF_EN_SHIFT          (0x00000000u)
#define CSL_H3A_PCR_AF_EN_RESETVAL       (0x00000000u)

/*----AF_EN Tokens----*/
#define CSL_H3A_PCR_AF_EN_DISABLE        (0x00000000u)
#define CSL_H3A_PCR_AF_EN_ENABLE         (0x00000001u)

#define CSL_H3A_PCR_RESETVAL             (0xFFC007F8u)

/* AFPAX1 */

#define CSL_H3A_AFPAX1_PAXW_MASK         (0x007F0000u)
#define CSL_H3A_AFPAX1_PAXW_SHIFT        (0x00000010u)
#define CSL_H3A_AFPAX1_PAXW_RESETVAL     (0x00000000u)

#define CSL_H3A_AFPAX1_PAXH_MASK         (0x0000007Fu)
#define CSL_H3A_AFPAX1_PAXH_SHIFT        (0x00000000u)
#define CSL_H3A_AFPAX1_PAXH_RESETVAL     (0x00000000u)

#define CSL_H3A_AFPAX1_RESETVAL          (0x00000000u)

/* AFPAX2 */

#define CSL_H3A_AFPAX2_AFINCV_MASK       (0x0001E000u)
#define CSL_H3A_AFPAX2_AFINCV_SHIFT      (0x0000000Du)
#define CSL_H3A_AFPAX2_AFINCV_RESETVAL   (0x00000000u)

#define CSL_H3A_AFPAX2_PAXVC_MASK        (0x00001FC0u)
#define CSL_H3A_AFPAX2_PAXVC_SHIFT       (0x00000006u)
#define CSL_H3A_AFPAX2_PAXVC_RESETVAL    (0x00000000u)

#define CSL_H3A_AFPAX2_PAXHC_MASK        (0x0000003Fu)
#define CSL_H3A_AFPAX2_PAXHC_SHIFT       (0x00000000u)
#define CSL_H3A_AFPAX2_PAXHC_RESETVAL    (0x00000000u)

#define CSL_H3A_AFPAX2_RESETVAL          (0x00000000u)

/* AFPAXSTART */

#define CSL_H3A_AFPAXSTART_PAXSH_MASK    (0x0FFF0000u)
#define CSL_H3A_AFPAXSTART_PAXSH_SHIFT   (0x00000010u)
#define CSL_H3A_AFPAXSTART_PAXSH_RESETVAL (0x00000000u)

#define CSL_H3A_AFPAXSTART_PAXSV_MASK    (0x00000FFFu)
#define CSL_H3A_AFPAXSTART_PAXSV_SHIFT   (0x00000000u)
#define CSL_H3A_AFPAXSTART_PAXSV_RESETVAL (0x00000000u)

#define CSL_H3A_AFPAXSTART_RESETVAL      (0x00000000u)

/* AFIIRSH */

#define CSL_H3A_AFIIRSH_IIRSH_MASK       (0x00000FFFu)
#define CSL_H3A_AFIIRSH_IIRSH_SHIFT      (0x00000000u)
#define CSL_H3A_AFIIRSH_IIRSH_RESETVAL   (0x00000000u)

#define CSL_H3A_AFIIRSH_RESETVAL         (0x00000000u)

/* AFBUFST */

#define CSL_H3A_AFBUFST_AFBUFST_MASK     (0xFFFFFFFFu)
#define CSL_H3A_AFBUFST_AFBUFST_SHIFT    (0x00000000u)
#define CSL_H3A_AFBUFST_AFBUFST_RESETVAL (0x00000000u)

#define CSL_H3A_AFBUFST_RESETVAL         (0x00000000u)

/* AFCOEF010 */

#define CSL_H3A_AFCOEF010_COEFF1_MASK    (0x0FFF0000u)
#define CSL_H3A_AFCOEF010_COEFF1_SHIFT   (0x00000010u)
#define CSL_H3A_AFCOEF010_COEFF1_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEF010_COEFF0_MASK    (0x00000FFFu)
#define CSL_H3A_AFCOEF010_COEFF0_SHIFT   (0x00000000u)
#define CSL_H3A_AFCOEF010_COEFF0_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEF010_RESETVAL       (0x00000000u)

/* AFCOEF032 */

#define CSL_H3A_AFCOEF032_COEFF3_MASK    (0x0FFF0000u)
#define CSL_H3A_AFCOEF032_COEFF3_SHIFT   (0x00000010u)
#define CSL_H3A_AFCOEF032_COEFF3_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEF032_COEFF2_MASK    (0x00000FFFu)
#define CSL_H3A_AFCOEF032_COEFF2_SHIFT   (0x00000000u)
#define CSL_H3A_AFCOEF032_COEFF2_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEF032_RESETVAL       (0x00000000u)

/* AFCOEFF054 */

#define CSL_H3A_AFCOEFF054_COEFF5_MASK   (0x0FFF0000u)
#define CSL_H3A_AFCOEFF054_COEFF5_SHIFT  (0x00000010u)
#define CSL_H3A_AFCOEFF054_COEFF5_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF054_COEFF4_MASK   (0x00000FFFu)
#define CSL_H3A_AFCOEFF054_COEFF4_SHIFT  (0x00000000u)
#define CSL_H3A_AFCOEFF054_COEFF4_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF054_RESETVAL      (0x00000000u)

/* AFCOEFF076 */

#define CSL_H3A_AFCOEFF076_COEFF7_MASK   (0x0FFF0000u)
#define CSL_H3A_AFCOEFF076_COEFF7_SHIFT  (0x00000010u)
#define CSL_H3A_AFCOEFF076_COEFF7_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF076_COEFF6_MASK   (0x00000FFFu)
#define CSL_H3A_AFCOEFF076_COEFF6_SHIFT  (0x00000000u)
#define CSL_H3A_AFCOEFF076_COEFF6_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF076_RESETVAL      (0x00000000u)

/* AFCOEFF098 */

#define CSL_H3A_AFCOEFF098_COEFF9_MASK   (0x0FFF0000u)
#define CSL_H3A_AFCOEFF098_COEFF9_SHIFT  (0x00000010u)
#define CSL_H3A_AFCOEFF098_COEFF9_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF098_COEFF8_MASK   (0x00000FFFu)
#define CSL_H3A_AFCOEFF098_COEFF8_SHIFT  (0x00000000u)
#define CSL_H3A_AFCOEFF098_COEFF8_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF098_RESETVAL      (0x00000000u)

/* AFCOEFF0010 */

#define CSL_H3A_AFCOEFF0010_COEFF10_MASK (0x00000FFFu)
#define CSL_H3A_AFCOEFF0010_COEFF10_SHIFT (0x00000000u)
#define CSL_H3A_AFCOEFF0010_COEFF10_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF0010_RESETVAL     (0x00000000u)

/* AFCOEF110 */

#define CSL_H3A_AFCOEF110_COEFF1_MASK    (0x0FFF0000u)
#define CSL_H3A_AFCOEF110_COEFF1_SHIFT   (0x00000010u)
#define CSL_H3A_AFCOEF110_COEFF1_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEF110_COEFF0_MASK    (0x00000FFFu)
#define CSL_H3A_AFCOEF110_COEFF0_SHIFT   (0x00000000u)
#define CSL_H3A_AFCOEF110_COEFF0_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEF110_RESETVAL       (0x00000000u)

/* AFCOEF132 */

#define CSL_H3A_AFCOEF132_COEFF3_MASK    (0x0FFF0000u)
#define CSL_H3A_AFCOEF132_COEFF3_SHIFT   (0x00000010u)
#define CSL_H3A_AFCOEF132_COEFF3_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEF132_COEFF2_MASK    (0x00000FFFu)
#define CSL_H3A_AFCOEF132_COEFF2_SHIFT   (0x00000000u)
#define CSL_H3A_AFCOEF132_COEFF2_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEF132_RESETVAL       (0x00000000u)

/* AFCOEFF154 */

#define CSL_H3A_AFCOEFF154_COEFF5_MASK   (0x0FFF0000u)
#define CSL_H3A_AFCOEFF154_COEFF5_SHIFT  (0x00000010u)
#define CSL_H3A_AFCOEFF154_COEFF5_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF154_COEFF4_MASK   (0x00000FFFu)
#define CSL_H3A_AFCOEFF154_COEFF4_SHIFT  (0x00000000u)
#define CSL_H3A_AFCOEFF154_COEFF4_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF154_RESETVAL      (0x00000000u)

/* AFCOEFF176 */

#define CSL_H3A_AFCOEFF176_COEFF7_MASK   (0x0FFF0000u)
#define CSL_H3A_AFCOEFF176_COEFF7_SHIFT  (0x00000010u)
#define CSL_H3A_AFCOEFF176_COEFF7_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF176_COEFF6_MASK   (0x00000FFFu)
#define CSL_H3A_AFCOEFF176_COEFF6_SHIFT  (0x00000000u)
#define CSL_H3A_AFCOEFF176_COEFF6_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF176_RESETVAL      (0x00000000u)

/* AFCOEFF198 */

#define CSL_H3A_AFCOEFF198_COEFF9_MASK   (0x0FFF0000u)
#define CSL_H3A_AFCOEFF198_COEFF9_SHIFT  (0x00000010u)
#define CSL_H3A_AFCOEFF198_COEFF9_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF198_COEFF8_MASK   (0x00000FFFu)
#define CSL_H3A_AFCOEFF198_COEFF8_SHIFT  (0x00000000u)
#define CSL_H3A_AFCOEFF198_COEFF8_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF198_RESETVAL      (0x00000000u)

/* AFCOEFF1010 */

#define CSL_H3A_AFCOEFF1010_COEFF10_MASK (0x00000FFFu)
#define CSL_H3A_AFCOEFF1010_COEFF10_SHIFT (0x00000000u)
#define CSL_H3A_AFCOEFF1010_COEFF10_RESETVAL (0x00000000u)

#define CSL_H3A_AFCOEFF1010_RESETVAL     (0x00000000u)

/* AEWWIN1 */

#define CSL_H3A_AEWWIN1_WINH_MASK        (0x7F000000u)
#define CSL_H3A_AEWWIN1_WINH_SHIFT       (0x00000018u)
#define CSL_H3A_AEWWIN1_WINH_RESETVAL    (0x00000000u)

#define CSL_H3A_AEWWIN1_WINW_MASK        (0x000FE000u)
#define CSL_H3A_AEWWIN1_WINW_SHIFT       (0x0000000Du)
#define CSL_H3A_AEWWIN1_WINW_RESETVAL    (0x00000000u)

#define CSL_H3A_AEWWIN1_WINVC_MASK       (0x00001FC0u)
#define CSL_H3A_AEWWIN1_WINVC_SHIFT      (0x00000006u)
#define CSL_H3A_AEWWIN1_WINVC_RESETVAL   (0x00000000u)

#define CSL_H3A_AEWWIN1_WINHC_MASK       (0x0000003Fu)
#define CSL_H3A_AEWWIN1_WINHC_SHIFT      (0x00000000u)
#define CSL_H3A_AEWWIN1_WINHC_RESETVAL   (0x00000000u)

#define CSL_H3A_AEWWIN1_RESETVAL         (0x00000000u)

/* AEWINSTART */

#define CSL_H3A_AEWINSTART_WINSV_MASK    (0x0FFF0000u)
#define CSL_H3A_AEWINSTART_WINSV_SHIFT   (0x00000010u)
#define CSL_H3A_AEWINSTART_WINSV_RESETVAL (0x00000000u)

#define CSL_H3A_AEWINSTART_WINSH_MASK    (0x00000FFFu)
#define CSL_H3A_AEWINSTART_WINSH_SHIFT   (0x00000000u)
#define CSL_H3A_AEWINSTART_WINSH_RESETVAL (0x00000000u)

#define CSL_H3A_AEWINSTART_RESETVAL      (0x00000000u)

/* AEWINBLK */

#define CSL_H3A_AEWINBLK_WINSV_MASK      (0x0FFF0000u)
#define CSL_H3A_AEWINBLK_WINSV_SHIFT     (0x00000010u)
#define CSL_H3A_AEWINBLK_WINSV_RESETVAL  (0x00000000u)

#define CSL_H3A_AEWINBLK_WINH_MASK       (0x0000007Fu)
#define CSL_H3A_AEWINBLK_WINH_SHIFT      (0x00000000u)
#define CSL_H3A_AEWINBLK_WINH_RESETVAL   (0x00000000u)

#define CSL_H3A_AEWINBLK_RESETVAL        (0x00000000u)

/* AEWSUBWIN */

#define CSL_H3A_AEWSUBWIN_AEWINCV_MASK   (0x00000F00u)
#define CSL_H3A_AEWSUBWIN_AEWINCV_SHIFT  (0x00000008u)
#define CSL_H3A_AEWSUBWIN_AEWINCV_RESETVAL (0x00000000u)

#define CSL_H3A_AEWSUBWIN_AEWINCH_MASK   (0x0000000Fu)
#define CSL_H3A_AEWSUBWIN_AEWINCH_SHIFT  (0x00000000u)
#define CSL_H3A_AEWSUBWIN_AEWINCH_RESETVAL (0x00000000u)

#define CSL_H3A_AEWSUBWIN_RESETVAL       (0x00000000u)

/* AEWBUFST */

#define CSL_H3A_AEWBUFST_AEWBUFST_MASK   (0xFFFFFFFFu)
#define CSL_H3A_AEWBUFST_AEWBUFST_SHIFT  (0x00000000u)
#define CSL_H3A_AEWBUFST_AEWBUFST_RESETVAL (0x00000000u)

#define CSL_H3A_AEWBUFST_RESETVAL        (0x00000000u)

#endif

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