📄 davincievm_arm.gel
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int i;
#define PSC_BASE 0x01C41000
#define PSC_EPCPR *( unsigned int* )( 0x01C41070 )
#define PSC_PTCMD *( unsigned int* )( 0x01C41120 )
#define PSC_PTSTAT *( unsigned int* )( 0x01C41128 )
#define PSC_PDSTAT0 *( unsigned int* )( 0x01C41200 )
#define PSC_PDSTAT1 *( unsigned int* )( 0x01C41204 )
#define PSC_PDCTL0 *( unsigned int* )( 0x01C41300 )
#define PSC_PDCTL1 *( unsigned int* )( 0x01C41304 )
#define PSC_EPCCR *( unsigned int* )( 0x01C41078 )
#define PSC_MDSTAT_BASE ( 0x01C41800 )
#define PSC_MDCTL_BASE ( 0x01C41A00 )
for( i = 0 ; i < 41 ; i++ )
*( unsigned int* )( PSC_MDCTL_BASE + 4 * i ) |= 0x0003; // Enable all 41 power domains
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 8 ) = 0x0000; // IEEE1394A - OFF
/*
* Set EMURSTIE to 1 on the following
*/
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 1 ) |= 0x0203; // VPSS MMR
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 5 ) |= 0x0203; // EMAC
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 6 ) |= 0x0203; // EMAC Wrapper
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 7 ) |= 0x0203; // MDIO
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 9 ) |= 0x0203; // USB
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 10 ) |= 0x0203; // ATA/CF
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 11 ) |= 0x0203; // VLYNQ
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 12 ) |= 0x0203; // HPI
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 13 ) |= 0x0203; // DDR2
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 14 ) |= 0x0203; // AEMIF
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 15 ) |= 0x0203; // MMC/SD
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 16 ) |= 0x0203; // MemoryStick
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 17 ) |= 0x0203; // ASP
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 26 ) |= 0x0203; // GPIO
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 40 ) |= 0x0203; // IMCOP
PSC_PTCMD = 0x0001; // Start power state transition for ALWAYSON
while( ( PSC_PTSTAT & 0x0001 ) != 0 ); // Wait for power state transtion to finish
PSC_PTCMD = 0x0002; // Start power state transition for DSP
while( ( PSC_PTSTAT & 0x0002 ) != 0 ); // Wait for power state transtion to finish
/*
* Clear EMURSTIE to 0 on the following
*/
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 1 ) &= 0x0003; // VPSS MMR
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 5 ) &= 0x0003; // EMAC
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 6 ) &= 0x0003; // EMAC Wrapper
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 7 ) &= 0x0003; // MDIO
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 9 ) &= 0x0003; // USB
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 10 ) &= 0x0003; // ATA/CF
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 11 ) &= 0x0003; // VLYNQ
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 12 ) &= 0x0003; // HPI
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 13 ) &= 0x0003; // DDR2
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 14 ) &= 0x0003; // AEMIF
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 15 ) &= 0x0003; // MMC/SD
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 16 ) &= 0x0003; // MemoryStick
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 17 ) &= 0x0003; // ASP
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 26 ) &= 0x0003; // GPIO
*( unsigned int* )( PSC_MDCTL_BASE + 4 * 40 ) &= 0x0003; // IMCOP
GEL_TextOut( "All power and clocks are turned on\n" );
}
/* ------------------------------------------------------------------------ *
* *
* setup_ddr2( ) *
* *
* *
* ------------------------------------------------------------------------ */
setup_ddr2( )
{
#define DDR_BASE 0x20000000
#define SDCFG *( unsigned int* )( 0x20000008 )
#define SDREF *( unsigned int* )( 0x2000000C )
#define SDTIM0 *( unsigned int* )( 0x20000010 )
#define SDTIM1 *( unsigned int* )( 0x20000014 )
#define DDRCTL *( unsigned int* )( 0x200000E4 )
#define PSC_BASE 0x01C41000
#define PSC_EPCPR *( unsigned int* )( 0x01C41070 )
#define PSC_PTCMD *( unsigned int* )( 0x01C41120 )
#define PSC_PTSTAT *( unsigned int* )( 0x01C41128 )
#define PSC_PDSTAT0 *( unsigned int* )( 0x01C41200 )
#define PSC_PDSTAT1 *( unsigned int* )( 0x01C41204 )
#define PSC_PDCTL0 *( unsigned int* )( 0x01C41300 )
#define PSC_PDCTL1 *( unsigned int* )( 0x01C41304 )
#define PSC_EPCCR *( unsigned int* )( 0x01C41078 )
#define PSC_MDSTAT_BASE ( 0x01C41800 )
#define PSC_MDCTL_BASE ( 0x01C41A00 )
#define PSC_MDSTAT_DDR *( unsigned int* )( PSC_MDSTAT_BASE + 4 * 13 )
#define PSC_MDCTL_DDR *( unsigned int* )( PSC_MDCTL_BASE + 4 * 13 )
//setup_psc_on( 0, 13 ); // Setup Power
/*
* DDR Initialization
*/
DDRCTL = 0x50006405; // DDR PHY Ctrl - DLL powered, ReadLatency=6
//SDCFG = 0x00008622; //0x00008632;// DDR Bank Cfg - 32-bit bus, CAS=3, 8 banks, 1024-word pages
SDCFG = 0x00008632;
SDTIM0 = 0x229229c9; // DDR Timing
SDTIM1 = 0x0012c722; // DDR Timing
//SDCFG = 0x00000622; // DDR Bank Cfg - disable timing reg access
SDCFG = 0x00000632; // DDR Bank Cfg - disable timing reg access
//SDREF = 0x000003D6; // DDR Refresh Ctrl - 126 MHz * 7.8us
SDREF = 0x0000041D; // DDR Refresh Ctrl - 135 MHz * 7.8us
/*
* Reset DDR2 PHY
*/
PSC_MDCTL_DDR &= 0xFFFFFFE0; // Clear state
PSC_MDCTL_DDR |= 0x00000001; // Set to SyncReset
PSC_PTCMD = 0x0001; // Start power state transition
while( ( PSC_PTSTAT & 0x0001 ) != 0 ); // Wait for power state transtion to finish
while( ( PSC_MDSTAT_DDR & 0x001F ) != 1 ); // Wait for module state syncreset
/*
* Enable DDR2 PHY
*/
PSC_MDCTL_DDR &= 0xFFFFFFE0; // Clear state
PSC_MDCTL_DDR |= 0x00000003; // Set to Enable
PSC_PTCMD = 0x0001; // Start power state transition
while( ( PSC_PTSTAT & 0x0001 ) != 0 ); // Wait for power state transtion to finish
while( ( PSC_MDSTAT_DDR & 0x001F ) != 3 ); // Wait for module state enable
GEL_TextOut( "DDR2 initialized for 32-bit Interface\n" );
}
/* ------------------------------------------------------------------------ *
* *
* setup_general_16bit_emif( ) *
* *
* ------------------------------------------------------------------------ */
setup_general_16bit_emif( )
{
#define AEMIF_BASE 0x01E00000
#define WAITCFG *( unsigned int* )( 0x01E00004 ) // Async Wait Cycle Config Register
#define ACFG2 *( unsigned int* )( 0x01E00010 ) // Async Bank1 Config Register
#define ACFG3 *( unsigned int* )( 0x01E00014 ) // Async Bank2 Config Register
#define ACFG4 *( unsigned int* )( 0x01E00018 ) // Async Bank3 Config Register
#define ACFG5 *( unsigned int* )( 0x01E0001C ) // Async Bank4 Config Register
#define NANDCTL *( unsigned int* )( 0x01E00060 ) // NAND Flash Control Register
WAITCFG = 0x00000000; // Asynchronous Wait Cycles Configuration Control Register
//ACFG2 = 0x3FFFFFFD; // Asynchronous Banks - MAX TIMEOUT
ACFG2 = 0x00900305;
ACFG3 = 0x3FFFFFFD;
ACFG4 = 0x3FFFFFFD;
ACFG5 = 0x3FFFFFFD;
NANDCTL = 0x00000000;
GEL_TextOut( "AEMIF initialized for 16-bit interface\n" );
}
/* ------------------------------------------------------------------------ *
* *
* turn_on_dsp( ) *
* *
* ------------------------------------------------------------------------ */
turn_on_dsp( )
{
unsigned int domainbit = 0x0002;
#define PSC_BASE 0x01C41000
#define PSC_EPCPR *( unsigned int* )( 0x01C41070 )
#define PSC_PTCMD *( unsigned int* )( 0x01C41120 )
#define PSC_PTSTAT *( unsigned int* )( 0x01C41128 )
#define PSC_PDSTAT0 *( unsigned int* )( 0x01C41200 )
#define PSC_PDSTAT1 *( unsigned int* )( 0x01C41204 )
#define PSC_PDCTL0 *( unsigned int* )( 0x01C41300 )
#define PSC_PDCTL1 *( unsigned int* )( 0x01C41304 )
#define PSC_EPCCR *( unsigned int* )( 0x01C41078 )
#define PSC_MDSTAT_BASE ( 0x01C41800 )
#define PSC_MDCTL_BASE ( 0x01C41A00 )
#define PSC_MDSTAT_DSP *( unsigned int* )( PSC_MDSTAT_BASE + 4 * 39 )
#define PSC_MDCTL_DSP *( unsigned int* )( PSC_MDCTL_BASE + 4 * 39 )
#define PSC_MDSTAT_IMCOP *( unsigned int* )( PSC_MDSTAT_BASE + 4 * 40 )
#define PSC_MDCTL_IMCOP *( unsigned int* )( PSC_MDCTL_BASE + 4 * 40 )
if ( ( PSC_MDSTAT_DSP & 0x001F ) != 0x0003 )
{
while( ( PSC_PTSTAT & domainbit ) != 0 ); // Wait for state transtion to finish
PSC_PDCTL1 |= 0x0001; // Turn ON power domain
PSC_MDCTL_DSP |= 0x0003; // Set DSP module state to enable
PSC_MDCTL_IMCOP |= 0x003; // Set IMCOP module state to enable
PSC_PTCMD = domainbit; // Start state transition
while( ( PSC_EPCPR & domainbit ) == 0 ); // Wait for external power request
/*
* Apply External Power if needed.
*/
PSC_PDCTL1 |= 0x0100; // Turn ON external power
while( ( PSC_PTSTAT & domainbit ) != 0 ); // Wait for state transtion to finish
}
GEL_TextOut( "DSP is On\n" );
}
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