📄 video_test.c

📁 TI的DM6446的硬件平台搭建的相关例子
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#include "davincievm_i2c.h"
#include "davincievm.h"

#define TVP5146_I2C_ADDR 0x5D

#define TVP5150_I2C_ADDR_L 0x5D
#define TVP5150_I2C_ADDR_H 0x5C

//#define TVP5146_I2C_RADDR 0xBB

Uint16 temp;
Uint32 temp1,temp2[5];
Uint16 tmp;


/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  tvp5146_rset                                                            *
 *                                                                          *
 *      Set codec register regnum to value regval                           *
 *                                                                          *
 * ------------------------------------------------------------------------ */
void tvp5150_rset( Uint8 regnum, Uint8 regval,Uint8 channel )
{
    Uint8 cmd[2];
    cmd[0] = regnum;    // 8-bit Register Address
    cmd[1] = regval;    // 8-bit Register Data
	switch (channel)
	{
		case 1:
    		temp=DAVINCIEVM_I2C_write( TVP5150_I2C_ADDR_L, cmd, 2);
			break;
		case 2:
			temp=DAVINCIEVM_I2C_write( TVP5150_I2C_ADDR_H, cmd, 2);
			break;
		case 3:
		{
			temp=DAVINCIEVM_I2C_write( TVP5150_I2C_ADDR_L, cmd, 2);
			temp=DAVINCIEVM_I2C_write( TVP5150_I2C_ADDR_H, cmd, 2);
			break;
		}
		default:
			break;		
	}
    //cmd[0]=cmd[1];
    //temp=DAVINCIEVM_I2C_write( TVP5146_I2C_ADDR, cmd, 1 );
	//DAVINCIEVM_I2C_write( TVP5146_I2C_ADDR, cmd, 1 );
}


/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  tvp5146_rget                                                            *
 *                                                                          *
 *      Return value of codec register regnum                               *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Uint8 tvp5150_rget( Uint8 regnum, Uint8 channel )
{
    Uint8 cmd[2];
    //Int16 i;

    cmd[0] = regnum;    // 8-bit Register Address
    cmd[1] = 0;         // 8-bit Register Data
	switch (channel)
	{
		case 1:
		{
    		DAVINCIEVM_I2C_write ( TVP5150_I2C_ADDR_L, cmd, 1 );
    		DAVINCIEVM_I2C_read ( TVP5150_I2C_ADDR_L, cmd, 1 );
			break;
    	}			
		case 2:
			DAVINCIEVM_I2C_write ( TVP5150_I2C_ADDR_H, cmd, 1 );
    		DAVINCIEVM_I2C_read ( TVP5150_I2C_ADDR_H, cmd, 1 );
			break;			
		case 3:
			DAVINCIEVM_I2C_write ( TVP5150_I2C_ADDR_L, cmd, 1 );
    		DAVINCIEVM_I2C_read ( TVP5150_I2C_ADDR_L, cmd, 1 );
			DAVINCIEVM_I2C_write ( TVP5150_I2C_ADDR_H, cmd, 1 );
    		DAVINCIEVM_I2C_read ( TVP5150_I2C_ADDR_H, cmd, 1 );
			break;
		default:
			break;
	}

    return cmd[0];
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  tvp5146_init( )                                                         *
 *                                                                          *
 *      Initialize the TVP5146                                              *
 *                                                                          *
 * ------------------------------------------------------------------------ */
void tvp5150_init(Uint8 channel,Uint8 mode)
{
   //DAVINCIEVM_waitusec( 1000 );        // wait 1 msec

    //DAVINCIEVM_waitusec( 1000 );        // wait 1 msec
//	tvp5146_rset( 0x05, 0x01 );
//	tvp5146_rset( 0x05, 0x00 );
	DAVINCIEVM_GPIO_setDirection(39,0);
	DAVINCIEVM_GPIO_setDirection(41,0);
	switch (channel)
	{
		case 1:
		{
			DAVINCIEVM_GPIO_setOutput(39,0);
			DAVINCIEVM_GPIO_setOutput(41,1);
			break;
		}
		case 2:
		{
			DAVINCIEVM_GPIO_setOutput(39,1);
			DAVINCIEVM_GPIO_setOutput(41,0);
			break;
		}
		case 3:
		{
			DAVINCIEVM_GPIO_setOutput(39,1);
			DAVINCIEVM_GPIO_setOutput(41,1);
			break;
		}
	}
	DAVINCIEVM_waitusec( 1000 );
	switch(mode)
	{
		case 1:
		{
    tvp5150_rset( 0x00, 0x00, channel );         // Input Video: CVBS   : VI_2_B
   // tvp5146_rset( 0x01, 0x15 );
	//tvp5146_rset( 0x02, 0x00 );
    tvp5150_rset( 0x03, 0x6d, channel );
    //tvp5146_rset( 0x03, 0x6d );         // NTSC
	//tvp5146_rset( 0x04, 0x00);
	//tvp5146_rset( 0x05, 0x00 );
	//tvp5146_rset( 0x06, 0x10 );
//	tvp5150_rset( 0x07, 0x10, channel );         //linger raw
	//tvp5146_rset( 0x08, 0x00 );
	tvp5150_rset( 0x09, 0x8B, channel );
	tvp5150_rset( 0x0a, 0x80, channel );
	tvp5150_rset( 0x0b, 0x00, channel );
	//tvp5146_rset( 0x0c, 0x80 );
    tvp5150_rset( 0x0D, 0x07, channel );         // Enabling clock & Y/CB/CR input format
	//tvp5146_rset( 0x0e, 0x00 );
	tvp5150_rset( 0x0F, 0x02, channel );
	//tvp5146_rset( 0x11, 0x00 );
	//tvp5146_rset( 0x12, 0x00 );
	//tvp5146_rset( 0x13, 0x00 );
	//tvp5146_rset( 0x14, 0x00 );
	tvp5150_rset( 0x15, 0x04, channel );
	//tvp5146_rset( 0x16, 0x80 );
	//tvp5146_rset( 0x18, 0x00 );
	tvp5150_rset( 0x19, 0x01, channel );                //linger raw
	//tvp5146_rset( 0x1a, 0x0c );
	tvp5150_rset( 0x1B, 0x14, channel );
	//tvp5146_rset( 0x1c, 0x00 );
	//tvp5146_rset( 0x1d, 0x00 );
//	tvp5146_rset( 0x1e, 0x00 );
//	tvp5146_rset( 0x28, 0x00 );


//	temp = tvp5146_rget(0x01);
		break;
		}
    	default:
		{
    tvp5150_rset( 0x00, 0x00, channel );         // Input Video: CVBS   : VI_2_B
   // tvp5146_rset( 0x01, 0x15 );
	//tvp5146_rset( 0x02, 0x00 );
    tvp5150_rset( 0x03, 0x6d, channel );
    //tvp5146_rset( 0x03, 0x6d );         // NTSC
	//tvp5146_rset( 0x04, 0x00);
	//tvp5146_rset( 0x05, 0x00 );
	//tvp5146_rset( 0x06, 0x10 );
//	tvp5150_rset( 0x07, 0x10, channel );         //linger raw
	//tvp5146_rset( 0x08, 0x00 );
	tvp5150_rset( 0x09, 0x8B, channel );
	tvp5150_rset( 0x0a, 0x80, channel );
	tvp5150_rset( 0x0b, 0x00, channel );
	//tvp5146_rset( 0x0c, 0x80 );
    tvp5150_rset( 0x0D, 0x07, channel );         // Enabling clock & Y/CB/CR input format
	//tvp5146_rset( 0x0e, 0x00 );
	tvp5150_rset( 0x0F, 0x02, channel );
	//tvp5146_rset( 0x11, 0x00 );
	//tvp5146_rset( 0x12, 0x00 );
	//tvp5146_rset( 0x13, 0x00 );
	//tvp5146_rset( 0x14, 0x00 );
	tvp5150_rset( 0x15, 0x05, channel );
	//tvp5146_rset( 0x16, 0x80 );
	//tvp5146_rset( 0x18, 0x00 );
	tvp5150_rset( 0x19, 0x01, channel );                //linger raw
	//tvp5146_rset( 0x1a, 0x0c );
	tvp5150_rset( 0x1B, 0x14, channel );
	//tvp5146_rset( 0x1c, 0x00 );
	//tvp5146_rset( 0x1d, 0x00 );
//	tvp5146_rset( 0x1e, 0x00 );
//	tvp5146_rset( 0x28, 0x00 );


//	temp = tvp5146_rget(0x01);
		break;
		}
	}
    DAVINCIEVM_waitusec( 1000 );        // wait 1 msec
}

#define NTSC 1

#if NTSC
    #define BASEP_X 0x7A // 122
    #define BASEP_Y 0x12 // 18
#elif PAL
    #define BASEP_X 0x84 // 132
    #define BASEP_Y 0x16 // 22
#endif

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  vpfe_init( )                                                            *
 *                                                                          *
 *  NTSC:                                                                   *
 *      Width:  720                                                         *
 *      Height: 480                                                         *
 *                                                                          *
 *                                                                          *
 * ------------------------------------------------------------------------ */

void vpfe_init( Uint32 buffer, Uint32 width, Uint32 height,Uint8 channel )
{
	switch (channel)
	{
		case 1:
		{
    VPFE_SYN_MODE   = 0x00032F87;   // interlaced, with VD pority as negative
//    VPFE_SYN_MODE   = 0x00031084;   //linger interlaced, with VD pority as negative
    VPFE_HD_VD_WID  = 0;
//    VPFE_PIX_LINES  = 0x02CF0271; 
	VPFE_PIX_LINES  = 0;  //linger 720x624
	//VPFE_PIX_LINES=0x020d0271;;

    /*
     *  sph = 1, nph = 1440, according to page 32-33 of the CCDC spec
     *  for BT.656 mode, this setting captures only the 720x480 of the
     *  active NTSV video window
     */
    VPFE_HORZ_INFO  = width << 1;   // Horizontal lines
    VPFE_HSIZE_OFF  = width << 1;   // Horizontal line offset
//    VPFE_HORZ_INFO  = width<< 1;   // Horizontal lines
//    VPFE_HSIZE_OFF  = 0;   // Horizontal line offset
    VPFE_VERT_START = 0;            // Vertical start line
    VPFE_VERT_LINES = height >> 1;  // Vertical lines
    VPFE_CULLING    = 0xFFFF00FF;   // Disable cullng

    /*
     *  Interleave the two fields 
     */
    VPFE_SDOFST     = 0x00000249;
    VPFE_SDR_ADDR   = buffer;
    VPFE_CLAMP      = 0;
    VPFE_DCSUB      = 0;
    VPFE_COLPTN     = 0xEE44EE44;
    VPFE_BLKCMP     = 0;
    VPFE_FPC_ADDR   = 0x86800000;
    VPFE_FPC        = 0;
    VPFE_VDINT      = 0;
    VPFE_ALAW       = 0;
    VPFE_REC656IF   = 0x00000003;
//	VPFE_REC656IF   = 0x00000002;  //linger

    /*
     *  Input format is Cb:Y:Cr:Y, w/ Y in odd-pixel position 
     */
//....

//    VPFE_CCDCFG     = 0x00000800;
//	VPFE_CCDCFG     = 0x00008800;
//    VPFE_FMTCFG     = 0;
//	VPFE_FMTCFG     = 0x00008000;  //linger
	VPFE_CCDCFG     = 0x00000800;
    VPFE_FMTCFG     = 0;

	//...

    VPFE_FMT_HORZ   = 0x000002D0;
    VPFE_FMT_VERT   = 0x00000240;//0x00000272;
    VPFE_FMT_ADDR0  = 0;
    VPFE_FMT_ADDR1  = 0;
    VPFE_FMT_ADDR2  = 0;
    VPFE_FMT_ADDR3  = 0;
    VPFE_FMT_ADDR4  = 0;
    VPFE_FMT_ADDR5  = 0;
    VPFE_FMT_ADDR6  = 0;
    VPFE_FMT_ADDR7  = 0;
    VPFE_PRGEVEN_0  = 0;
    VPFE_PRGEVEN_1  = 0;
    VPFE_PRGODD_0   = 0;
    VPFE_PRGODD_1   = 0;
    VPFE_VP_OUT     = 0x04E22D00;
    VPFE_PCR        = 0x00000001;   // Enable CCDC
			break;
		}
		case 2:
		{
//    VPFE_SYN_MODE   = 0x00032F84;   // interlaced, with VD pority as negative
    VPFE_SYN_MODE   = 0x00030084;   //linger interlaced, with VD pority as negative
    VPFE_HD_VD_WID  = 0;
//    VPFE_PIX_LINES  = 0x02CF0271; 
	VPFE_PIX_LINES  = 0;  //linger 720x625
	//VPFE_PIX_LINES=0x020d0271;

    /*
     *  sph = 1, nph = 1440, according to page 32-33 of the CCDC spec
     *  for BT.656 mode, this setting captures only the 720x480 of the
     *  active NTSV video window
     */
//    VPFE_HORZ_INFO  = width << 1;   // Horizontal lines
	VPFE_HORZ_INFO  = width << 1;   // Horizontal lines
//	VPFE_HORZ_INFO  = 0x6C0;   // Horizontal lines
    VPFE_HSIZE_OFF  = width << 1;   // Horizontal line offset
//    VPFE_HSIZE_OFF  = 0x6C0;   // Horizontal line offset
    VPFE_VERT_START = 0;            // Vertical start line
//    VPFE_VERT_LINES = height >> 1;  // Vertical lines
	VPFE_VERT_LINES = height >> 1;  // Vertical lines
    VPFE_CULLING    = 0xFFFF00FF;   // Disable cullng

    /*
     *  Interleave the two fields 
     */
    VPFE_SDOFST     = 0x00000249;
    VPFE_SDR_ADDR   = buffer;
    VPFE_CLAMP      = 0;
    VPFE_DCSUB      = 0;
    VPFE_COLPTN     = 0xEE44EE44;
    VPFE_BLKCMP     = 0;
    VPFE_FPC_ADDR   = 0x86800000;
    VPFE_FPC        = 0;
    VPFE_VDINT      = 0;
    VPFE_ALAW       = 0;
//    VPFE_REC656IF   = 0x00000003;
	VPFE_REC656IF   = 0x00000002;  //linger

    /*
     *  Input format is Cb:Y:Cr:Y, w/ Y in odd-pixel position 
     */
//    VPFE_CCDCFG     = 0x00000800;
	VPFE_CCDCFG     = 0x00000800;
//    VPFE_FMTCFG     = 0;
	VPFE_FMTCFG     = 0x00008000;  //linger
    VPFE_FMT_HORZ   = 0x000002D0;
    VPFE_FMT_VERT   = 0x00000272;
    VPFE_FMT_ADDR0  = 0;
    VPFE_FMT_ADDR1  = 0;
    VPFE_FMT_ADDR2  = 0;
    VPFE_FMT_ADDR3  = 0;
    VPFE_FMT_ADDR4  = 0;
    VPFE_FMT_ADDR5  = 0;
    VPFE_FMT_ADDR6  = 0;
    VPFE_FMT_ADDR7  = 0;
    VPFE_PRGEVEN_0  = 0;
    VPFE_PRGEVEN_1  = 0;
    VPFE_PRGODD_0   = 0;
    VPFE_PRGODD_1   = 0;
    VPFE_VP_OUT     = 0x04e22D00;
    VPFE_PCR        = 0x00000001;   // Enable CCDC
			break;			
		}
		case 3:
		{
//    VPFE_SYN_MODE   = 0x00032F84;   // interlaced, with VD pority as negative
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