davincievm_ddr.c

TI的DM6446的硬件平台搭建的相关例子

/*
 *  Copyright 2005 by Spectrum Digital Incorporated.
 *  All rights reserved. Property of Spectrum Digital Incorporated.
 *
 *  Not for distribution.
 */

/*
 *  Board Setup ( for ARM and/or DSP )
 *
 */

#include "davincievm.h"

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  DAVINCIEVM_DDR_init( )                                                  *
 *                                                                          *
 *                                                                          *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_DDR_init( )
{
    /*
     *  DDR Initialization @ 135MHz
     */
    DDRCTL = 0x50006435;    // put PHY in reset

    DAVINCIEVM_wait( 100 );

    DDRCTL = 0x50006405;    // Program PHY Control Register
    SDCFG  = 0x00008632;    // Program SDRAM Bank Config Register
    SDTIM0 = 0x229229c9;    // Program SDRAM Timing Control Register
    SDTIM1 = 0x0012c722;
    SDCFG  = 0x00000632;    // Program SDRAM Bank Config Register
    SDREF  = 0x0000041d;    // Program SDRAM Refresh Control Register

    return 0;
}