📄 davincievm_emif.c
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/*
* Copyright 2005 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*
* Not for distribution.
*/
/*
* Board Setup ( for ARM and/or DSP )
*
*/
#ifdef DSP_SIDE
#include "davincievm_emif.h"
#else
#include "davincievm_emif.h"
#include "csl_emif.h"
#endif
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_EMIF_init( ) *
* *
* Initialize ASYNC EMIF to have MAX timeout *
* *
* @ 459 MHz, AEMIF clock is set to ( 76.5 MHz or 13.1 ns ) *
* @ 594 MHz, AEMIF clock is set to ( 99 MHz or 10.1 ns ) *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_EMIF_init( )
{
#ifdef ARM_SIDE
AEMIF_ACFG2 = 0 // [Normal Mode][Turbo Mode]
| ( 0 << 31 ) // Select Strobe [ Normal ]
| ( 0 << 30 ) // Extended Wait [ Disabled ]
| ( 15 << 26 ) // Write Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 20 ) // Write Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 17 ) // Write Hold [ 91.5 ns ][ 70.7 ns ]
| ( 15 << 13 ) // Read Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 7 ) // Read Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 4 ) // Read Hold [ 91.5 ns ][ 70.7 ns ]
| ( 3 << 2 ) // Turn Around [ 39.2 ns ][ 30.3 ns ]
| ( 1 << 0 ) // Bus Size [ 16-bit Bus ]
;
AEMIF_ACFG3 = 0 // [Normal Mode][Turbo Mode]
| ( 0 << 31 ) // Select Strobe [ Normal ]
| ( 0 << 30 ) // Extended Wait [ Disabled ]
| ( 15 << 26 ) // Write Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 20 ) // Write Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 17 ) // Write Hold [ 91.5 ns ][ 70.7 ns ]
| ( 15 << 13 ) // Read Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 7 ) // Read Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 4 ) // Read Hold [ 91.5 ns ][ 70.7 ns ]
| ( 3 << 2 ) // Turn Around [ 39.2 ns ][ 30.3 ns ]
| ( 1 << 0 ) // Bus Size [ 16-bit Bus ]
;
AEMIF_ACFG4 = 0 // [Normal Mode][Turbo Mode]
| ( 0 << 31 ) // Select Strobe [ Normal ]
| ( 0 << 30 ) // Extended Wait [ Disabled ]
| ( 15 << 26 ) // Write Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 20 ) // Write Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 17 ) // Write Hold [ 91.5 ns ][ 70.7 ns ]
| ( 15 << 13 ) // Read Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 7 ) // Read Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 4 ) // Read Hold [ 91.5 ns ][ 70.7 ns ]
| ( 3 << 2 ) // Turn Around [ 39.2 ns ][ 30.3 ns ]
| ( 1 << 0 ) // Bus Size [ 16-bit Bus ]
;
AEMIF_ACFG5 = 0 // [Normal Mode][Turbo Mode]
| ( 0 << 31 ) // Select Strobe [ Normal ]
| ( 0 << 30 ) // Extended Wait [ Disabled ]
| ( 15 << 26 ) // Write Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 20 ) // Write Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 17 ) // Write Hold [ 91.5 ns ][ 70.7 ns ]
| ( 15 << 13 ) // Read Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 7 ) // Read Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 4 ) // Read Hold [ 91.5 ns ][ 70.7 ns ]
| ( 3 << 2 ) // Turn Around [ 39.2 ns ][ 30.3 ns ]
| ( 1 << 0 ) // Bus Size [ 16-bit Bus ]
;
AEMIF_NANDFCR = 0
| ( 0 << 11 ) // NAND ECC for CS5 [ No ]
| ( 0 << 10 ) // NAND ECC for CS4 [ No ]
| ( 0 << 9 ) // NAND ECC for CS3 [ No ]
| ( 0 << 8 ) // NAND ECC for CS2 [ No ]
| ( 0 << 3 ) // NAND Flash on CS5[ No ]
| ( 0 << 2 ) // NAND Flash on CS4[ No ]
| ( 0 << 1 ) // NAND Flash on CS3[ No ]
| ( 0 << 0 ) // NAND Flash on CS2[ No ]
;
return 0;
#elif DSP_SIDE
AEMIF_ACFG2 = 0 // [Normal Mode][Turbo Mode]
| ( 0 << 31 ) // Select Strobe [ Normal ]
| ( 0 << 30 ) // Extended Wait [ Disabled ]
| ( 15 << 26 ) // Write Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 20 ) // Write Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 17 ) // Write Hold [ 91.5 ns ][ 70.7 ns ]
| ( 15 << 13 ) // Read Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 7 ) // Read Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 4 ) // Read Hold [ 91.5 ns ][ 70.7 ns ]
| ( 3 << 2 ) // Turn Around [ 39.2 ns ][ 30.3 ns ]
| ( 1 << 0 ) // Bus Size [ 16-bit Bus ]
;
AEMIF_ACFG3 = 0 // [Normal Mode][Turbo Mode]
| ( 0 << 31 ) // Select Strobe [ Normal ]
| ( 0 << 30 ) // Extended Wait [ Disabled ]
| ( 15 << 26 ) // Write Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 20 ) // Write Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 17 ) // Write Hold [ 91.5 ns ][ 70.7 ns ]
| ( 15 << 13 ) // Read Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 7 ) // Read Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 4 ) // Read Hold [ 91.5 ns ][ 70.7 ns ]
| ( 3 << 2 ) // Turn Around [ 39.2 ns ][ 30.3 ns ]
| ( 1 << 0 ) // Bus Size [ 16-bit Bus ]
;
AEMIF_ACFG4 = 0 // [Normal Mode][Turbo Mode]
| ( 0 << 31 ) // Select Strobe [ Normal ]
| ( 0 << 30 ) // Extended Wait [ Disabled ]
| ( 15 << 26 ) // Write Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 20 ) // Write Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 17 ) // Write Hold [ 91.5 ns ][ 70.7 ns ]
| ( 15 << 13 ) // Read Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 7 ) // Read Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 4 ) // Read Hold [ 91.5 ns ][ 70.7 ns ]
| ( 3 << 2 ) // Turn Around [ 39.2 ns ][ 30.3 ns ]
| ( 1 << 0 ) // Bus Size [ 16-bit Bus ]
;
AEMIF_ACFG5 = 0 // [Normal Mode][Turbo Mode]
| ( 0 << 31 ) // Select Strobe [ Normal ]
| ( 0 << 30 ) // Extended Wait [ Disabled ]
| ( 15 << 26 ) // Write Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 20 ) // Write Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 17 ) // Write Hold [ 91.5 ns ][ 70.7 ns ]
| ( 15 << 13 ) // Read Setup [ 196.1 ns ][ 151.5 ns ]
| ( 31 << 7 ) // Read Strobe [ 405.2 ns ][ 313.1 ns ]
| ( 7 << 4 ) // Read Hold [ 91.5 ns ][ 70.7 ns ]
| ( 3 << 2 ) // Turn Around [ 39.2 ns ][ 30.3 ns ]
| ( 1 << 0 ) // Bus Size [ 16-bit Bus ]
;
AEMIF_NANDFCR = 0
| ( 0 << 11 ) // NAND ECC for CS5 [ No ]
| ( 0 << 10 ) // NAND ECC for CS4 [ No ]
| ( 0 << 9 ) // NAND ECC for CS3 [ No ]
| ( 0 << 8 ) // NAND ECC for CS2 [ No ]
| ( 0 << 3 ) // NAND Flash on CS5[ No ]
| ( 0 << 2 ) // NAND Flash on CS4[ No ]
| ( 0 << 1 ) // NAND Flash on CS3[ No ]
| ( 0 << 0 ) // NAND Flash on CS2[ No ]
;
return 0;
#endif
}
/* ------------------------------------------------------------------------ *
* *
* DAVINCIEVM_EMIF_config( ) *
* *
* Configure ASYNC EMIF timing registers *
* *
* acfg2 <- Chip Select 2 timing config *
* acfg3 <- Chip Select 3 timing config *
* acfg4 <- Chip Select 4 timing config *
* acfg5 <- Chip Select 5 timing config *
* *
* ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_EMIF_config( Uint32 acfg2, Uint32 acfg3, Uint32 acfg4, Uint32 acfg5 )
{
AEMIF_ACFG2 = acfg2;
AEMIF_ACFG3 = acfg3;
AEMIF_ACFG4 = acfg4;
AEMIF_ACFG5 = acfg5;
return 0;
}
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