davincievm_pll.c

TI的DM6446的硬件平台搭建的相关例子

/*
 *  Copyright 2005 by Spectrum Digital Incorporated.
 *  All rights reserved. Property of Spectrum Digital Incorporated.
 *
 *  Not for distribution.
 */

/*
 *  Board Setup ( for ARM and/or DSP )
 *
 */

#include "davincievm_pll.h"

#ifdef ARM_SIDE

    #include "csl_pllc.h"

#elif DSP_SIDE

#endif

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  DAVINCIEVM_enablePll1( clock_source, pll_mult )                         *
 *                                                                          *
 *      clock_source    <- 0: Onchip Oscillator                             *
 *                         1: External Oscillator                           *
 *                                                                          *
 *      pll_mult        <- 16: Normal mode ( For PLL1 )                     *
 *                         22: Turbo mode  ( For PLL1 )                     *
 *                         X:  Range 0-63                                   *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_enablePll1( Uint16 clock_source, Uint16 pll_mult )
{
    #ifdef ARM_SIDE

        CSL_Status      status;
        CSL_PllcHandle  pllc_handle;
        CSL_PllcObj     pllc_obj;
        CSL_PllcParam   pllc_param;
        CSL_PllcHwSetup pll_hwsetup;

        Uint32 pll_ctl;

        pll_hwsetup.divEnable   = CSL_PLLC_DIVEN_POSTDIV
                                | CSL_PLLC_DIVEN_PLLDIV1
                                | CSL_PLLC_DIVEN_PLLDIV2
                                | CSL_PLLC_DIVEN_PLLDIV3
                                | CSL_PLLC_DIVEN_PLLDIV4
                                | CSL_PLLC_DIVEN_PLLDIV5
                                ;
        pll_hwsetup.preDiv      = 0;        // No Pre Divider
        pll_hwsetup.pllM        = pll_mult; // Pll multiplier
        pll_hwsetup.postDiv     = 0;        // Post Divider @ 1
        pll_hwsetup.pllDiv1     = 0;        // Fixed divider @ 1
        pll_hwsetup.pllDiv2     = 1;        // Fixed divider @ 2
        pll_hwsetup.pllDiv3     = 2;        // Fixed divider @ 3
        pll_hwsetup.pllDiv4     = 3;        // Fixed divider @ 4
        pll_hwsetup.pllDiv5     = 5;        // Fixed divider @ 6
        pll_hwsetup.pllDiv6     = 0;        //
        pll_hwsetup.pllDiv7     = 0;        //
        pll_hwsetup.pllDiv8     = 0;        //
        pll_hwsetup.oscDiv1     = 0;        //
        pll_hwsetup.phaseAlign  = 0;        //
        pll_hwsetup.extendSetup = 0;        //

        CSL_pllcInit( 0 );
        pllc_handle = CSL_pllcOpen( &pllc_obj, 0, &pllc_param, &status );
        status |= CSL_pllcHwSetup( pllc_handle, &pll_hwsetup );

        pll_ctl = 0x00000049;

        status |= CSL_pllcHwControl( pllc_handle, CSL_PLLC_CMD_PLLCONTROL, &pll_ctl );

        CSL_pllcClose( pllc_handle );

        return 0;

    #elif DSP_SIDE

    #endif
}

/* ------------------------------------------------------------------------ *
 *                                                                          *
 *  DAVINCIEVM_enablePll2( clock_source, pll_mult, divider1, divider2 )     *
 *                                                                          *
 *      clock_source    <- 0: Onchip Oscillator                             *
 *                         1: External Oscillator                           *
 *                                                                          *
 *      pll_mult        <- 16: Normal mode ( For PLL1 )                     *
 *                         22: Turbo mode  ( For PLL1 )                     *
 *                         X:  Range 0-63                                   *
 *                                                                          *
 *      divider1        <- VPSS divider ( For PLL2 )                        *
 *                                                                          *
 *      divider2        <- DDR2 divider ( For PLL2 )                        *
 *                                                                          *
 * ------------------------------------------------------------------------ */
Int16 DAVINCIEVM_enablePll2( Uint16 clock_source, Uint16 pll_mult,
                             Uint16 divider1, Uint16 divider2 )
{
    #ifdef ARM_SIDE

        CSL_Status      status;
        CSL_PllcHandle  pllc_handle;
        CSL_PllcObj     pllc_obj;
        CSL_PllcParam   pllc_param;
        CSL_PllcHwSetup pll_hwsetup;

        Uint32 pll_ctl;

        pll_hwsetup.divEnable   = CSL_PLLC_DIVEN_POSTDIV
                                | CSL_PLLC_DIVEN_PLLDIV1
                                | CSL_PLLC_DIVEN_PLLDIV2
                                ;
        pll_hwsetup.preDiv      = 0;        // No Pre Divider
        pll_hwsetup.pllM        = pll_mult; // Pll multiplier
        pll_hwsetup.postDiv     = 0;        // Post Divider @ 1
        pll_hwsetup.pllDiv1     = divider1; // Pll divider 1
        pll_hwsetup.pllDiv2     = divider2; // Pll divider 2
        pll_hwsetup.pllDiv3     = 0;        //
        pll_hwsetup.pllDiv4     = 0;        //
        pll_hwsetup.pllDiv5     = 0;        //
        pll_hwsetup.pllDiv6     = 0;        //
        pll_hwsetup.pllDiv7     = 0;        //
        pll_hwsetup.pllDiv8     = 0;        //
        pll_hwsetup.oscDiv1     = 0;        //
        pll_hwsetup.phaseAlign  = 0;        //
        pll_hwsetup.extendSetup = 0;        //

        CSL_pllcInit( 0 );
        pllc_handle = CSL_pllcOpen( &pllc_obj, 1, &pllc_param, &status );
        status |= CSL_pllcHwSetup( pllc_handle, &pll_hwsetup );

        pll_ctl = 0x00000049;
        status |= CSL_pllcHwControl( pllc_handle, CSL_PLLC_CMD_PLLCONTROL, &pll_ctl );
        CSL_pllcClose( pllc_handle );

        return 0;

    #elif DSP_SIDE

    #endif
}