📄 myuart.lst
字号:
0000008E 4800 LDR R0,=0x10000000
00000090 7001 STRB R1,[R0,#0x0]
61: reg_CR=reg_CR|0x1E;
ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 6
00000092 4800 LDR R0,=0x10000000
00000094 7800 LDRB R0,[R0,#0x0]
00000096 1C01 MOV R1,R0
00000098 201E MOV R0,#0x1E
0000009A 4301 ORR R1,R0
0000009C 0609 LSL R1,R1,#0x18
0000009E 0E09 LSR R1,R1,#0x18
000000A0 4800 LDR R0,=0x10000000
000000A2 7001 STRB R1,[R0,#0x0]
63: }
000000A4 L_5:
000000A4 4800 LDR R0,=0x10000000
000000A6 7800 LDRB R0,[R0,#0x0]
000000A8 2101 MOV R1,#0x1
000000AA 4008 AND R0,R1
000000AC 2801 CMP R0,#0x1
000000AE D0ED BEQ L_7 ; T=0x0000008C
66: }
000000B0 BC08 POP {R3}
000000B2 4718 BX R3
000000B4 ENDP ; 'Init?T'
*** CODE SEGMENT '?PR?Delay?T?myuart':
69: void Delay(int dly)
00000000 ---- Variable 'dly' assigned to Register 'R0' ----
70: {
00000000 ; SCOPE-START
72: for(;dly>0;dly--)
00000000 E005 B L_11 ; T=0x0000000E
73: for(j=0;j<50;j++){};
00000002 L_18:
00000002 2100 MOV R1,#0x0
00000004 ---- Variable 'j' assigned to Register 'R1' ----
00000004 L_14:
00000004 3101 ADD R1,#0x1
00000006 1C0A MOV R2,R1 ; j
00000008 2A32 CMP R2,#0x32 ; j
0000000A DBFB BLT L_14 ; T=0x00000004
0000000C 3801 SUB R0,#0x1
0000000E L_11:
0000000E 1C01 MOV R1,R0 ; dly
00000010 2900 CMP R1,#0x0 ; dly
00000012 DCF6 BGT L_18 ; T=0x00000002
00000014 ; SCOPE-END
74: }
00000014 4770 BX R14
00000016 ENDP ; 'Delay?T'
*** CODE SEGMENT '?PR?Reset?T?myuart':
78: void Reset()
00000000 B500 PUSH {LR}
80: GP0DAT=0x02000000;
00000002 4800 LDR R1,=0x2000000
00000004 4800 LDR R0,=0xFFFFF420
00000006 6001 STR R1,[R0,#0x0]
81: Delay(2000);
00000008 4800 LDR R0,=0x7D0
0000000A F7FF BL Delay?T ; T=0x0001 (1)
0000000C FFF9 BL Delay?T ; T=0x0001 (2)
82: GP0DAT=0x02020000;
0000000E 4800 LDR R1,=0x2020000
00000010 4800 LDR R0,=0xFFFFF420
00000012 6001 STR R1,[R0,#0x0]
83: }
00000014 BC08 POP {R3}
00000016 4718 BX R3
00000018 ENDP ; 'Reset?T'
*** CODE SEGMENT '?PR?sendmessage?T?myuart':
ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 7
86: void sendmessage(uchar a0,uchar a1,uchar a2,uchar a3,uchar a4,uchar a5,uchar a6,uchar a7,uchar a8,uchar a9)
00000000 B470 PUSH {R4-R6}
00000002 ---- Variable 'a3' assigned to Register 'R3' ----
00000002 ---- Variable 'a2' assigned to Register 'R2' ----
00000002 ---- Variable 'a1' assigned to Register 'R1' ----
00000002 1C05 MOV R5,R0 ; a0
00000004 ---- Variable 'a0' assigned to Register 'R5' ----
87: {
00000004 ; SCOPE-START
88: uchar len=0;
00000004 2400 MOV R4,#0x0
00000006 ---- Variable 'len' assigned to Register 'R4' ----
89: while(reg_SR&0X10);
00000006 L_19:
00000006 4800 LDR R0,=0x10000002
00000008 7800 LDRB R0,[R0,#0x0]
0000000A 2610 MOV R6,#0x10
0000000C 4230 TST R0,R6
0000000E D1FA BNE L_19 ; T=0x00000006
90: while((reg_SR&0X08)==0);
00000010 L_23:
00000010 4800 LDR R0,=0x10000002
00000012 7800 LDRB R0,[R0,#0x0]
00000014 2608 MOV R6,#0x8
00000016 4230 TST R0,R6
00000018 D0FA BEQ L_23 ; T=0x00000010
91: while((reg_SR&0X04)==0);
0000001A L_27:
0000001A 4800 LDR R0,=0x10000002
0000001C 7800 LDRB R0,[R0,#0x0]
0000001E 2604 MOV R6,#0x4
00000020 4230 TST R0,R6
00000022 D0FA BEQ L_27 ; T=0x0000001A
92: reg_Sendone=a0;
00000024 1C2C MOV R4,R5 ; a0
00000026 4800 LDR R0,=0x1000000A
00000028 7004 STRB R4,[R0,#0x0]
93: reg_Sendtwo=a1;
0000002A 1C0C MOV R4,R1 ; a1
0000002C 4800 LDR R0,=0x1000000B
0000002E 7004 STRB R4,[R0,#0x0]
94: len=a1&0x0f;
00000030 1C08 MOV R0,R1 ; a1
00000032 0604 LSL R4,R0,#0x18 ; a1
00000034 0E24 LSR R4,R4,#0x18
00000036 200F MOV R0,#0xF
00000038 4004 AND R4,R0
0000003A 0624 LSL R4,R4,#0x18
0000003C 0E24 LSR R4,R4,#0x18
95: switch(len)
0000003E 1C20 MOV R0,R4 ; len
00000040 2800 CMP R0,#0x0 ; len
00000042 D100 BEQ $+4
00000044 E0C0 B L_31 ; T=0x000001C8
00000048 2802 CMP R0,#0x2 ; len
0000004A D011 BEQ L_35 ; T=0x00000070
0000004C 2803 CMP R0,#0x3 ; len
0000004E D016 BEQ L_36 ; T=0x0000007E
00000050 2804 CMP R0,#0x4 ; len
00000052 D01F BEQ L_37 ; T=0x00000094
00000054 2805 CMP R0,#0x5 ; len
00000056 D02C BEQ L_38 ; T=0x000000B2
00000058 2806 CMP R0,#0x6 ; len
0000005A D03D BEQ L_39 ; T=0x000000D8
0000005C 2807 CMP R0,#0x7 ; len
0000005E D052 BEQ L_40 ; T=0x00000106
ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 8
00000060 2808 CMP R0,#0x8 ; len
00000062 D06B BEQ L_41 ; T=0x0000013C
00000064 2801 CMP R0,#0x1 ; len
00000066 D000 BNE $+4
00000068 E087 B L_33 ; T=0x0000017A
98: case 0x01: reg_Senddata1=a2;break;
0000006C L_34:
0000006C 1C11 MOV R1,R2 ; a2
0000006E 4800 LDR R0,=0x1000000C
00000070 7001 STRB R1,[R0,#0x0]
00000072 E0A9 B L_31 ; T=0x000001C8
99: case 0x02: reg_Senddata1=a2;reg_Senddata2=a3;break;
00000074 L_35:
00000074 1C11 MOV R1,R2 ; a2
00000076 4800 LDR R0,=0x1000000C
00000078 7001 STRB R1,[R0,#0x0]
0000007A 1C19 MOV R1,R3 ; a3
0000007C 4800 LDR R0,=0x1000000D
0000007E 7001 STRB R1,[R0,#0x0]
00000080 E0A2 B L_31 ; T=0x000001C8
100: case 0x03: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;break;
00000082 L_36:
00000082 1C11 MOV R1,R2 ; a2
00000084 4800 LDR R0,=0x1000000C
00000086 7001 STRB R1,[R0,#0x0]
00000088 1C19 MOV R1,R3 ; a3
0000008A 4800 LDR R0,=0x1000000D
0000008C 7001 STRB R1,[R0,#0x0]
0000008E A800 ADD R0,R13,#0x0
00000090 7801 LDRB R1,[R0,#0x0] ; a4
00000092 4800 LDR R0,=0x1000000E
00000094 7001 STRB R1,[R0,#0x0]
00000096 E097 B L_31 ; T=0x000001C8
101: case 0x04: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;break;
00000098 L_37:
00000098 1C11 MOV R1,R2 ; a2
0000009A 4800 LDR R0,=0x1000000C
0000009C 7001 STRB R1,[R0,#0x0]
0000009E 1C19 MOV R1,R3 ; a3
000000A0 4800 LDR R0,=0x1000000D
000000A2 7001 STRB R1,[R0,#0x0]
000000A4 A800 ADD R0,R13,#0x0
000000A6 7801 LDRB R1,[R0,#0x0] ; a4
000000A8 4800 LDR R0,=0x1000000E
000000AA 7001 STRB R1,[R0,#0x0]
000000AC A801 ADD R0,R13,#0x4
000000AE 7801 LDRB R1,[R0,#0x0] ; a5
000000B0 4800 LDR R0,=0x1000000F
000000B2 7001 STRB R1,[R0,#0x0]
000000B4 E088 B L_31 ; T=0x000001C8
102: case 0x05: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;reg_Senddata5=a6;break;
000000B6 L_38:
000000B6 1C11 MOV R1,R2 ; a2
000000B8 4800 LDR R0,=0x1000000C
000000BA 7001 STRB R1,[R0,#0x0]
000000BC 1C19 MOV R1,R3 ; a3
000000BE 4800 LDR R0,=0x1000000D
000000C0 7001 STRB R1,[R0,#0x0]
000000C2 A800 ADD R0,R13,#0x0
000000C4 7801 LDRB R1,[R0,#0x0] ; a4
000000C6 4800 LDR R0,=0x1000000E
000000C8 7001 STRB R1,[R0,#0x0]
000000CA A801 ADD R0,R13,#0x4
000000CC 7801 LDRB R1,[R0,#0x0] ; a5
000000CE 4800 LDR R0,=0x1000000F
000000D0 7001 STRB R1,[R0,#0x0]
ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 9
000000D2 A802 ADD R0,R13,#0x8
000000D4 7801 LDRB R1,[R0,#0x0] ; a6
000000D6 4800 LDR R0,=0x10000010
000000D8 7001 STRB R1,[R0,#0x0]
000000DA E075 B L_31 ; T=0x000001C8
103: case 0x06: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;reg_Senddata5=a6;reg_Senddata6=a
-7;break;
000000DC L_39:
000000DC 1C11 MOV R1,R2 ; a2
000000DE 4800 LDR R0,=0x1000000C
000000E0 7001 STRB R1,[R0,#0x0]
000000E2 1C19 MOV R1,R3 ; a3
000000E4 4800 LDR R0,=0x1000000D
000000E6 7001 STRB R1,[R0,#0x0]
000000E8 A800 ADD R0,R13,#0x0
000000EA 7801 LDRB R1,[R0,#0x0] ; a4
000000EC 4800 LDR R0,=0x1000000E
000000EE 7001 STRB R1,[R0,#0x0]
000000F0 A801 ADD R0,R13,#0x4
000000F2 7801 LDRB R1,[R0,#0x0] ; a5
000000F4 4800 LDR R0,=0x1000000F
000000F6 7001 STRB R1,[R0,#0x0]
000000F8 A802 ADD R0,R13,#0x8
000000FA 7801 LDRB R1,[R0,#0x0] ; a6
000000FC 4800 LDR R0,=0x10000010
000000FE 7001 STRB R1,[R0,#0x0]
00000100 A803 ADD R0,R13,#0xC
00000102 7801 LDRB R1,[R0,#0x0] ; a7
00000104 4800 LDR R0,=0x10000011
00000106 7001 STRB R1,[R0,#0x0]
00000108 E05E B L_31 ; T=0x000001C8
104: case 0x07: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;reg_Senddata5=a6;reg_Senddata6=a
-7;reg_Senddata7=a8;break;
0000010A L_40:
0000010A 1C11 MOV R1,R2 ; a2
0000010C 4800 LDR R0,=0x1000000C
0000010E 7001 STRB R1,[R0,#0x0]
00000110 1C19 MOV R1,R3 ; a3
00000112 4800 LDR R0,=0x1000000D
00000114 7001 STRB R1,[R0,#0x0]
00000116 A800 ADD R0,R13,#0x0
00000118 7801 LDRB R1,[R0,#0x0] ; a4
0000011A 4800 LDR R0,=0x1000000E
0000011C 7001 STRB R1,[R0,#0x0]
0000011E A801 ADD R0,R13,#0x4
00000120 7801 LDRB R1,[R0,#0x0] ; a5
00000122 4800 LDR R0,=0x1000000F
00000124 7001 STRB R1,[R0,#0x0]
00000126 A802 ADD R0,R13,#0x8
00000128 7801 LDRB R1,[R0,#0x0] ; a6
0000012A 4800 LDR R0,=0x10000010
0000012C 7001 STRB R1,[R0,#0x0]
0000012E A803 ADD R0,R13,#0xC
00000130 7801 LDRB R1,[R0,#0x0] ; a7
00000132 4800 LDR R0,=0x10000011
00000134 7001 STRB R1,[R0,#0x0]
00000136 A804 ADD R0,R13,#0x10
00000138 7801 LDRB R1,[R0,#0x0] ; a8
0000013A 4800 LDR R0,=0x10000012
0000013C 7001 STRB R1,[R0,#0x0]
0000013E E043 B L_31 ; T=0x000001C8
105: case 0x08: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;reg_Senddata5=a6;reg_Senddata6=a
-7;reg_Senddata7=a8;reg_Senddata8=a9;break;
00000140 L_41:
00000140 1C11 MOV R1,R2 ; a2
00000142 4800 LDR R0,=0x1000000C
ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 10
00000144 7001 STRB R1,[R0,#0x0]
00000146 1C19 MOV R1,R3 ; a3
00000148 4800 LDR R0,=0x1000000D
0000014A 7001 STRB R1,[R0,#0x0]
0000014C A800 ADD R0,R13,#0x0
0000014E 7801 LDRB R1,[R0,#0x0] ; a4
00000150 4800 LDR R0,=0x1000000E
00000152 7001 STRB R1,[R0,#0x0]
00000154 A801 ADD R0,R13,#0x4
00000156 7801 LDRB R1,[R0,#0x0] ; a5
00000158 4800 LDR R0,=0x1000000F
0000015A 7001 STRB R1,[R0,#0x0]
0000015C A802 ADD R0,R13,#0x8
0000015E 7801 LDRB R1,[R0,#0x0] ; a6
00000160 4800 LDR R0,=0x10000010
00000162 7001 STRB R1,[R0,#0x0]
00000164 A803 ADD R0,R13,#0xC
00000166 7801 LDRB R1,[R0,#0x0] ; a7
00000168 4800 LDR R0,=0x10000011
0000016A 7001 STRB R1,[R0,#0x0]
0000016C A804 ADD R0,R13,#0x10
0000016E 7801 LDRB R1,[R0,#0x0] ; a8
00000170 4800 LDR R0,=0x10000012
00000172 7001 STRB R1,[R0,#0x0]
00000174 A805 ADD R0,R13,#0x14
00000176 7801 LDRB R1,[R0,#0x0] ; a9
00000178 4800 LDR R0,=0x10000013
0000017A 7001 STRB R1,[R0,#0x0]
0000017C E024 B L_31 ; T=0x000001C8
106: default: reg_Sendtwo=reg_Sendtwo&0xe8;reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;reg_S
-enddata5=a6;reg_Senddata6=a7;reg_Senddata7=a8;reg_Senddata8=a9;break;
0000017E L_33:
0000017E 4800 LDR R0,=0x1000000B
00000180 7800 LDRB R0,[R0,#0x0]
00000182 1C01 MOV R1,R0
00000184 20E8 MOV R0,#0xE8
00000186 4001 AND R1,R0
00000188 0609 LSL R1,R1,#0x18
0000018A 0E09 LSR R1,R1,#0x18
0000018C 4800 LDR R0,=0x1000000B
0000018E 7001 STRB R1,[R0,#0x0]
00000190 1C11 MOV R1,R2 ; a2
00000192 4800 LDR R0,=0x1000000C
00000194 7001 STRB R1,[R0,#0x0]
00000196 1C19 MOV R1,R3 ; a3
00000198 4800 LDR R0,=0x1000000D
0000019A 7001 STRB R1,[R0,#0x0]
0000019C A800 ADD R0,R13,#0x0
0000019E 7801 LDRB R1,[R0,#0x0] ; a4
000001A0 4800 LDR R0,=0x1000000E
000001A2 7001 STRB R1,[R0,#0x0]
000001A4 A801 ADD R0,R13,#0x4
000001A6 7801 LDRB R1,[R0,#0x0] ; a5
000001A8 4800 LDR R0,=0x1000000F
000001AA 7001 STRB R1,[R0,#0x0]
000001AC A802 ADD R0,R13,#0x8
000001AE 7801 LDRB R1,[R0,#0x0] ; a6
000001B0 4800 LDR R0,=0x10000010
000001B2 7001 STRB R1,[R0,#0x0]
000001B4 A803 ADD R0,R13,#0xC
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