📄 myuart.lst
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ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 1
ARM COMPILER V2.42, COMPILATION OF MODULE myuart
OBJECT MODULE PLACED IN myuart.OBJ
COMPILER INVOKED BY: C:\Keil\ARM\BIN\CA.exe myuart.c THUMB BROWSE DEBUG TABS(4)
stmt level source
1
2 #include <ADuC7026.h>
3 #include <sja1000.h>
4
5
6 #define uchar unsigned char
7
8
9 uchar iRecData[10];
10 uchar flagdata=0;
11 uchar dlc;
12
13
14
15 void Delay(int);
16 void Reset();
17 void rsvmessage();
18 void sendmessage(uchar,uchar,uchar,uchar,uchar,uchar,uchar,uchar,uchar,uchar);
19
20
21 void Init()
22 {
23 1
24 1 GP1CON=0x11;
25 1 GP2CON=0x22222222;
26 1 GP3CON=0x22222222;
27 1 GP4CON=0x22222222;
28 1
29 1
30 1 XMCFG = 0x01;
31 1 XM0CON = 0x01;
32 1 XM0PAR = 0x70FF;
33 1
34 1 COMCON0=0x080;
35 1 COMDIV0=0x088;
36 1 COMDIV1=0x000;
37 1 COMCON0=0x007;
38 1
39 1
40 1 Reset();
41 1
42 1 Delay(2000);
43 1
44 1 while((reg_CR&0x01)==0x00) //进入复位模式
45 1 {
46 2 reg_CR=reg_CR|0x01;
47 2
48 2 }
49 1
50 1 reg_CDR=0x41; //时钟分频寄存器，控制CLKOUT的输出频率，BASIC模式，CLKOUT输出fosc/2
51 1 reg_AMR=0xF0; //验收屏蔽寄存器，全部屏蔽
52 1 reg_ACR=0x07; //验收代码寄存器，与报文标志码的高8位相等
53 1 reg_BTR0=0x80; //总线时序寄存器0，系统的时钟周期Tscl是2Tclk同步跳转宽度3Tscl
54 1 reg_BTR1=0xFA; //总线时序寄存器1，总线采样3次，时间段1=11Tscl，时间段2=8Tscl
55 1 reg_OCR=0x1A;
56 1
57 1
58 1 while((reg_CR&0x01)==0x01)
59 1 {
ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 2
60 2 reg_CR=reg_CR&0x00;
61 2 reg_CR=reg_CR|0x1E;
62 2
63 2 }
64 1
65 1
66 1 }
67
68
69 void Delay(int dly)
70 {
71 1 int j;
72 1 for(;dly>0;dly--)
73 1 for(j=0;j<50;j++){};
74 1 }
75
76 /****************************************sja1000软件复位************************************/
77
78 void Reset()
79 {
80 1 GP0DAT=0x02000000;
81 1 Delay(2000);
82 1 GP0DAT=0x02020000;
83 1 }
84
85
86 void sendmessage(uchar a0,uchar a1,uchar a2,uchar a3,uchar a4,uchar a5,uchar a6,uchar a7,uchar a8,uchar a
-9)
87 {
88 1 uchar len=0;
89 1 while(reg_SR&0X10);
90 1 while((reg_SR&0X08)==0);
91 1 while((reg_SR&0X04)==0);
92 1 reg_Sendone=a0;
93 1 reg_Sendtwo=a1;
94 1 len=a1&0x0f;
95 1 switch(len)
96 1 {
97 2 case 0x00: break;
98 2 case 0x01: reg_Senddata1=a2;break;
99 2 case 0x02: reg_Senddata1=a2;reg_Senddata2=a3;break;
100 2 case 0x03: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;break;
101 2 case 0x04: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;break;
102 2 case 0x05: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;reg_Senddata5=a6;break;
103 2 case 0x06: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;reg_Senddata5=a6;reg_Sen
-ddata6=a7;break;
104 2 case 0x07: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;reg_Senddata5=a6;reg_Sen
-ddata6=a7;reg_Senddata7=a8;break;
105 2 case 0x08: reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=a5;reg_Senddata5=a6;reg_Sen
-ddata6=a7;reg_Senddata7=a8;reg_Senddata8=a9;break;
106 2 default: reg_Sendtwo=reg_Sendtwo&0xe8;reg_Senddata1=a2;reg_Senddata2=a3;reg_Senddata3=a4;reg_Senddata4=
-a5;reg_Senddata5=a6;reg_Senddata6=a7;reg_Senddata7=a8;reg_Senddata8=a9;break;
107 2 }
108 1 reg_CMR=0X01;
109 1 }
110
111 void rsvmessage()
112 {
113 1 uchar i;
114 1 uchar flag_IR;
115 1 if(reg_SR&0x03)
116 1 {
117 2 flag_IR=reg_IR;
118 2 if(flag_IR&0x01)
119 2 {
120 3 do{}while(reg_SR&0x10);
ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 3
121 3 iRecData[0]=reg_Rsvone;
122 3 iRecData[1]=reg_Rsvtwo;
123 3 dlc=iRecData[1]&0x0f;
124 3 for(i=0;i<dlc;i++)
125 3 {
126 4 iRecData[i+2]=*(®_Rsvdata1+i);
127 4 }
128 3 reg_CMR=0x04;
129 3 flagdata=1;
130 3 }
131 2 else
132 2 {
133 3 if(reg_SR&0x02) reg_CMR=0x0c;
134 3 }
135 2 }
136 1 }
137
138
139 uchar hex2ascii(uchar toconv)
140 {
141 1 if (toconv<0x0A)
142 1 {
143 2 toconv += 0x30;
144 2 }
145 1 else
146 1 {
147 2 toconv += 0x37;
148 2 }
149 1
150 1 return (toconv);
151 1 }
152
153
154 void senddata(uchar to_send) {
155 1 while(!(0x020==(COMSTA0 & 0x020))){}
156 1 COMTX = 0x0A; //Output LF
157 1 while(!(0x020==(COMSTA0 & 0x020))){}
158 1 COMTX = 0x0D; //Output CR
159 1 while(!(0x020==(COMSTA0 & 0x020))){}
160 1 COMTX = hex2ascii ((to_send >> 4) & 0x0F);
161 1 while(!(0x020==(COMSTA0 & 0x020))){}
162 1 COMTX = hex2ascii (to_send & 0x0F);
163 1 }
164
165
166 void main()
167 {
168 1 int k=1;
169 1 uchar temp1=1;
170 1 Init();
171 1
172 1 sendmessage(0x39,0x08,0x01,0x02,0x03,0x04,0x05,0x06,0x06,0x08);
173 1 Delay(1);
174 1 while(temp1)
175 1 {
176 2 sendmessage(0x37,0x08,k,0x02,0x03,0x05,0x05,0x06,0x06,0x08);
177 2 Delay(100000);
178 2 Delay(100000);
179 2 Delay(100000);
180 2 k++;
181 2 if(k==100)k=1;
182 2 }
183 1
184 1 }
185
ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 4
ASSEMBLY LISTING OF GENERATED OBJECT CODE
*** EXTERNALS:
EXTERN NUMBER (__startup)
*** PUBLICS:
PUBLIC Delay?T
PUBLIC Reset?T
PUBLIC rsvmessage?T
PUBLIC sendmessage?T
PUBLIC Init?T
PUBLIC hex2ascii?T
PUBLIC senddata?T
PUBLIC main
PUBLIC iRecData
PUBLIC flagdata
PUBLIC dlc
*** DATA SEGMENT '?DT0?myuart':
00000000 iRecData:
00000000 DS 10
0000000A flagdata:
0000000A BEGIN_INIT
0000000A 00 DB 0x0
0000000B END_INIT
0000000B dlc:
0000000B DS 1
*** CODE SEGMENT '?PR?Init?T?myuart':
21: void Init()
00000000 B500 PUSH {LR}
24: GP1CON=0x11;
00000002 2111 MOV R1,#0x11
00000004 4800 LDR R0,=0xFFFFF404
00000006 6001 STR R1,[R0,#0x0]
25: GP2CON=0x22222222;
00000008 4800 LDR R1,=0x22222222
0000000A 4800 LDR R0,=0xFFFFF408
0000000C 6001 STR R1,[R0,#0x0]
26: GP3CON=0x22222222;
0000000E 4800 LDR R0,=0xFFFFF40C
00000010 6001 STR R1,[R0,#0x0]
27: GP4CON=0x22222222;
00000012 4800 LDR R0,=0xFFFFF410
00000014 6001 STR R1,[R0,#0x0]
30: XMCFG = 0x01;
00000016 2101 MOV R1,#0x1
00000018 4800 LDR R0,=0xFFFFF000
0000001A 6001 STR R1,[R0,#0x0]
31: XM0CON = 0x01;
0000001C 4800 LDR R0,=0xFFFFF010
0000001E 6001 STR R1,[R0,#0x0]
32: XM0PAR = 0x70FF;
00000020 4800 LDR R1,=0x70FF
00000022 4800 LDR R0,=0xFFFFF020
00000024 6001 STR R1,[R0,#0x0]
34: COMCON0=0x080;
00000026 2180 MOV R1,#0x80
00000028 4800 LDR R0,=0xFFFF070C
0000002A 6001 STR R1,[R0,#0x0]
35: COMDIV0=0x088;
0000002C 2188 MOV R1,#0x88
0000002E 4800 LDR R0,=0xFFFF0700
00000030 6001 STR R1,[R0,#0x0]
36: COMDIV1=0x000;
ARM COMPILER V2.42, myuart 16/09/08 08:08:57 PAGE 5
00000032 2100 MOV R1,#0x0
00000034 4800 LDR R0,=0xFFFF0704
00000036 6001 STR R1,[R0,#0x0]
37: COMCON0=0x007;
00000038 2107 MOV R1,#0x7
0000003A 4800 LDR R0,=0xFFFF070C
0000003C 6001 STR R1,[R0,#0x0]
40: Reset();
0000003E F7FF BL Reset?T ; T=0x0001 (1)
00000040 FFDF BL Reset?T ; T=0x0001 (2)
42: Delay(2000);
00000042 4800 LDR R0,=0x7D0
00000044 F7FF BL Delay?T ; T=0x0001 (1)
00000046 FFDC BL Delay?T ; T=0x0001 (2)
44: while((reg_CR&0x01)==0x00) //进入复位模式
00000048 E008 B L_1 ; T=0x0000005C
0000004A L_3:
46: reg_CR=reg_CR|0x01;
0000004A 4800 LDR R0,=0x10000000
0000004C 7800 LDRB R0,[R0,#0x0]
0000004E 1C01 MOV R1,R0
00000050 2001 MOV R0,#0x1
00000052 4301 ORR R1,R0
00000054 0609 LSL R1,R1,#0x18
00000056 0E09 LSR R1,R1,#0x18
00000058 4800 LDR R0,=0x10000000
0000005A 7001 STRB R1,[R0,#0x0]
48: }
0000005C L_1:
0000005C 4800 LDR R0,=0x10000000
0000005E 7800 LDRB R0,[R0,#0x0]
00000060 2101 MOV R1,#0x1
00000062 4208 TST R0,R1
00000064 D0F1 BEQ L_3 ; T=0x0000004A
50: reg_CDR=0x41; //时钟分频寄存器，控制CLKOUT的输出频率，BASIC模式，CLKOUT输出fosc/2
00000066 2141 MOV R1,#0x41
00000068 4800 LDR R0,=0x1000001F
0000006A 7001 STRB R1,[R0,#0x0]
51: reg_AMR=0xF0; //验收屏蔽寄存器，全部屏蔽
0000006C 21F0 MOV R1,#0xF0
0000006E 4800 LDR R0,=0x10000005
00000070 7001 STRB R1,[R0,#0x0]
52: reg_ACR=0x07; //验收代码寄存器，与报文标志码的高8位相等
00000072 2107 MOV R1,#0x7
00000074 4800 LDR R0,=0x10000004
00000076 7001 STRB R1,[R0,#0x0]
53: reg_BTR0=0x80; //总线时序寄存器0，系统的时钟周期Tscl是2Tclk同步跳转宽度3Tscl
00000078 2180 MOV R1,#0x80
0000007A 4800 LDR R0,=0x10000006
0000007C 7001 STRB R1,[R0,#0x0]
54: reg_BTR1=0xFA; //总线时序寄存器1，总线采样3次，时间段1=11Tscl，时间段2=8Tscl
0000007E 21FA MOV R1,#0xFA
00000080 4800 LDR R0,=0x10000007
00000082 7001 STRB R1,[R0,#0x0]
55: reg_OCR=0x1A;
00000084 211A MOV R1,#0x1A
00000086 4800 LDR R0,=0x10000008
00000088 7001 STRB R1,[R0,#0x0]
58: while((reg_CR&0x01)==0x01)
0000008A E00B B L_5 ; T=0x000000A4
0000008C L_7:
60: reg_CR=reg_CR&0x00;
0000008C 2100 MOV R1,#0x0
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