startup.s

网上一个朋对UCGUI整作的一个简单分析, 大家看看,虽然不是很详细, 但比较有整体性.

.text
	.align 4 
	.global begin
	.type begin,function
begin:
	@set the IRQ stack
	mov 	r0, #0xd2          @IRQMode
	msr	cpsr_c,r0 	   @IRQMode
	ldr	sp,=IRQstack_beg
	
        mov	r0, #211   					@ make sure svc mode
	msr	CPSR_c, r0					@ and all irqs disabled
        adr	r5, startup_data			
        ldmia	r5, {r5, r8, sp}			@ Setup bss and stack , r5 is length

        /*  Copy data sections to their new home.  */
        /* r8 is bss addr */
        /*  Clear BSS */
	
1:      mov	r4, #0
        str	r4, [r8],#4
	sub     r5, r5, #1	
	cmp 	r5, #0
        bgt	1b
	
        /*  Pretend we know what our processor code is (for arm_id)   */

@@@	ldr     r2, =0x41000000
@@@	orr	r2, r2, #0x7000		@ FIXME --> 0x41007000

	ldr	r2, L_AT91_SF_CIDR
	ldr	r2, [r2]		@ read processor id

	str     r2, pid_adr
	/* MACH_TYPE_ATMEL is 89 0x59 */
	mov     r2, #89
	str     r2, mid_adr
	
	/* at91_init*/
	mov fp, #0
	bl	init_kernel
	
        mov fp, #0
        b	start_kernel
	
   @----------------------------------------------------------------------
/*
	.align  2
        .global ARMDisableInt
	.type    ARMDisableInt,function
ARMDisableInt:
         STMDB   sp!, {r0}
         MRS     r0, CPSR
         ORR     r0, r0, #0x80		@NoInterrupt
         MSR     CPSR_c, r0
         LDMIA   sp!, {r0}
	 MOV     pc, lr

	
    @------------------------------------------------------------------------
        .align  2
        .global ARMEnableInt
        .type    ARMEnableInt,function
ARMEnableInt:
        STMDB   sp!, {r0}
        MRS     r0, CPSR
        BIC     r0, r0, #0x80		@NoInterrupt
        MSR     CPSR_c, r0
        LDMIA   sp!, {r0}
        MOV     pc, lr
*/

@------------------------------------------------------------------------
        .align  2
        .global AT91_IRQHandler 
        .type    AT91_IRQHandler,function

AT91_IRQHandler:
	@Interrupt Handler Prologue
	SUB	lr, lr, #4
	STMFD	sp!, {r0-r12, lr}		@; push registers and return address
	MRS	r4, SPSR			@; get SPSR
	STMFD	sp!, {r4}			@; push SPSR
	@; End Interrupt Handler Prologue
	@; Call main IRQ service dispatcher
	BL do_IRQ
	
	/* chy test ------------
	LDR	r12, =swap_context_flag 
	LDR	r11, [r12]
	TST	r11, #1
	BEQ	2f
	MOV r11, #0
	STR	r11, [r12]
	B	IRQContextSwap
	------------------ */
	
	@; Interrupt Handler Epilogue
2:	LDMFD	sp!, {r4}			@; pop SPSR	
	MSR	SPSR_c, r4			@; restore SPSR
	LDMFD	sp!, {r0-r12, pc}^		@; restore registers and RFI
	@; End Interrupt Handler Epilogue
	@;
	@; End of IRQHandler
	@;

L_AT91_SF_CIDR: .long	0xfff00000

startup_data:   
	       .word	  4096
	       .word      stack_beg
	       .word	  bss_beg
pid_adr:       .word 	  proc_id
mid_adr:       .word	  mach_id
		
.data
	.align 2
proc_id: .word 0
mach_id: .word 0

	.align 2
	.type stack_beg,object
	.size stack_beg,4096
stack_beg:
	.word  0
	.space 4096
stak_end:
	.word	0
	.space 4096
IRQstack_beg:
	.word	0
	.space	4096
IRQstack_end:
	.word	0
	.space	4096
.bss
	.align 2
	.type bss_beg,object
	.size bss_beg,4096
bss_beg:
	.word 0
	.space 4096