sysinit.c

coldfire的mcf5329的程序

/*
 * File:        sysinit.c
 * Purpose:     M5329EVB Reset Configuration
 *
 * Notes:
 *
 */

#include "common.h"
#include "uart.h"
#include "clock.h"
#include "m5329evb.h"

/********************************************************************/

void scm_init(void);
void fbcs_init(void);
void sdramc_init(void);
void gpio_init(void);
void eport_init(void);
void wtm_init(void);

/********************************************************************/

/* Actual system clock frequency */
int sys_clk_khz;
int sys_clk_mhz;

/********************************************************************/
void
sysinit (void)
{
	sys_clk_khz = clock_pll(SYS_CLK_KHZ,0);
	sys_clk_mhz = sys_clk_khz/1000;
	
	
	wtm_init();
    sdramc_init();
	scm_init();
    gpio_init();
    uart_init(TERMINAL_PORT, sys_clk_khz, TERMINAL_BAUD,0);
    fbcs_init();
    eport_init();   
         
}
/********************************************************************/
void
wtm_init (void)
{
	/* Disable watchdog timer */
	
	MCF_WTM_WCR = 0;

}
/********************************************************************/
void
scm_init (void)
{

	/* All masters are trusted */
    MCF_SCM_MPR0 = 0x77777777;
    
    /* Allow supervisor/user, read/write, and trusted/untrusted
       access to all slaves */
       
    MCF_SCM_PACRA = 0;
    MCF_SCM_PACRB = 0;
    MCF_SCM_PACRC = 0;
    MCF_SCM_PACRD = 0;
    MCF_SCM_PACRE = 0;
    MCF_SCM_PACRF = 0;
    MCF_SCM_PACRG = 0;
    MCF_SCM_PACRH = 0;

}
/********************************************************************/
void
fbcs_init (void)
{

	MCF_GPIO_PAR_CS = 0x0000003E;

    /* Latch chip select */
    MCF_FBCS1_CSAR = 0x10080000;
/*    MCF_FBCS1_CSCR = (MCF_FBCS_CSCR_PS_16
                    | MCF_FBCS_CSCR_AA
                    | 0x00000200
                    | MCF_FBCS_CSCR_WS(3)
                    | MCF_FBCS_CSCR_ASET(2)
                    | MCF_FBCS_CSCR_RDAH(2)
                    | MCF_FBCS_CSCR_WRAH(2));
*/
	MCF_FBCS1_CSCR = 0x002A3780;  
    MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_2M
                    | MCF_FBCS_CSMR_V);                    

    /* Boot Flash connected to FBCS0 */
    MCF_FBCS0_CSAR = FLASH_ADDRESS;
    MCF_FBCS0_CSCR = (MCF_FBCS_CSCR_PS_16
    				| MCF_FBCS_CSCR_BEM
                    | MCF_FBCS_CSCR_AA
                    | 0x00000200
                    | MCF_FBCS_CSCR_WS(0x7));
    MCF_FBCS0_CSMR = (MCF_FBCS_CSMR_BAM_32M
                    | MCF_FBCS_CSMR_V);
}
/********************************************************************/

void
sdramc_init (void)
{

	/*
	 * Check to see if the SDRAM has already been initialized
	 * by a run control tool
	 */
	if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
	{

		/* SDRAM chip select initialization */
		
		/* Initialize SDRAM chip select */
        MCF_SDRAMC_SDCS0 = (0
            | MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS)
            | MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE)
            );
            

		/* 
         * Basic configuration and initialization 
         */
         
        MCF_SDRAMC_SDCFG1 = (0
			| MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5 ))
			| MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)
			| MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))
			| MCF_SDRAMC_SDCFG1_ACT2RW((int)((SDRAM_TRCD ) + 0.5))
			| MCF_SDRAMC_SDCFG1_PRE2ACT((int)((SDRAM_TRP ) + 0.5))
			| MCF_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC) ) + 0.5))
			| MCF_SDRAMC_SDCFG1_WTLAT(3)
            );
		MCF_SDRAMC_SDCFG2 = (0
			| MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL/2 + 1)
			| MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL/2 + SDRAM_TWR)
			| MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL/2 -1.0)+0.5))
			| MCF_SDRAMC_SDCFG2_BL(SDRAM_BL-1)
            );

            
		/* 
         * Precharge and enable write to SDMR 		  
         */
        MCF_SDRAMC_SDCR = (0
			| MCF_SDRAMC_SDCR_MODE_EN
			| MCF_SDRAMC_SDCR_CKE
			| MCF_SDRAMC_SDCR_DDR
			| MCF_SDRAMC_SDCR_MUX(1)
			| MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))
			| MCF_SDRAMC_SDCR_PS_16
			| MCF_SDRAMC_SDCR_IPALL
            );            
            

		/* 
         * Write extended mode register 
         */
		MCF_SDRAMC_SDMR = (0
			| MCF_SDRAMC_SDMR_BNKAD_LEMR
			| MCF_SDRAMC_SDMR_AD(0x0)
			| MCF_SDRAMC_SDMR_CMD
            );
		
		/* 
         * Write mode register and reset DLL 
         */
		MCF_SDRAMC_SDMR = (0
			| MCF_SDRAMC_SDMR_BNKAD_LMR
			| MCF_SDRAMC_SDMR_AD(0x163)
			| MCF_SDRAMC_SDMR_CMD
            );
				
		/* 
         * Execute a PALL command 
         */
		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
		
		/* 
         * Perform two REF cycles 
         */
		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
		MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
			
		/* 
         * Write mode register and clear reset DLL 
         */
		MCF_SDRAMC_SDMR = (0
			| MCF_SDRAMC_SDMR_BNKAD_LMR
			| MCF_SDRAMC_SDMR_AD(0x063)
			| MCF_SDRAMC_SDMR_CMD        
            );
				
		/* 
         * Enable auto refresh and lock SDMR 
         */
		MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN;
        MCF_SDRAMC_SDCR |= (0
			| MCF_SDRAMC_SDCR_REF
			| MCF_SDRAMC_SDCR_DQS_OE(0xC) 
            );
            
	}

}
/********************************************************************/
void
gpio_init(void)
{
    /* Enable UART0 pins */
    MCF_GPIO_PAR_UART = ( 0
//	    | MCF_GPIO_PAR_UART_PAR_UCTS0_UCTS0
//	    | MCF_GPIO_PAR_UART_PAR_URTS0_URTS0
	    | MCF_GPIO_PAR_UART_PAR_URXD0
	    | MCF_GPIO_PAR_UART_PAR_UTXD0 );
	    
	/* Enable FEC pins */
	
//	MCF_GPIO_PAR_FEC = ( 0
//					| MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC
//					| MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC );
					
//	MCF_GPIO_PAR_FECI2C = ( 0
//					| MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC
//					| MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO );	    
    
}
/********************************************************************/
void
eport_init(void)
{
	/*
	 * Allow interrupts from IRQ7 (black button)
	 */

	/* Set IRQ7 to be rising edge triggered */
	MCF_EPORT_EPPAR = MCF_EPORT_EPPAR_EPPA7(MCF_EPORT_EPPAR_EPPA7_RISING);

	/* Enable EPORT interrupt 7 requests */
	MCF_EPORT_EPIER = MCF_EPORT_EPIER_EPIE7;

}
/********************************************************************/