vgacore.vhd

This is interface VGA with monitor

-------------------------------------------------------------------------------
-- vgacore.vhd
--
-- Author(s):     Ashley Partis and Jorgen Peddersen 
-- Based largely on a version on the XESS (www.xess.com) page.  Thanks to XESS.
-- Created:       Jan 2001
-- Last Modified: Feb 2001
-- 
-- Creates VGA timing signals to a monitor, timings are currently for 72Hz @
-- 800 * 600.  To change the resolution or refresh rate, change the value of 
-- the constants and the generics to whatever is desired.  Changing the 
-- resolution and / or refresh also means the clock speed may have to change 
-- (currently based off a 50MHz clock).
--
-------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity vgacore is
	generic (
		H_SIZE : integer := 800;					-- horizontal size of input image, MAX 800
		V_SIZE : integer := 600						-- vertical size of input image, MAX 600
	);
	port
	(
		reset: in std_logic;						-- asynchronous active low reset
		clock: in std_logic;						-- clock
		hsyncb: buffer std_logic;					-- horizontal (line) sync
		vsyncb: out std_logic;						-- vertical (frame) sync
		latch: out STD_LOGIC;						-- latches new rgb value
		enable: out STD_LOGIC;						-- enable/ground RGB output lines
		hloc: out std_logic_vector(9 downto 0);		-- horizontal address to be decoded for video RAM
		vloc: out std_logic_vector(9 downto 0)		-- vertical address to be decoded for video RAM
	);
end vgacore;

architecture vgacore_arch of vgacore is

-- one of the sync signals
--
--                    |<------- Active Region ------------>|<----------- Blanking Region ---------->|
--                    |           (Pixels)                 |                                        |
--                    |                                    |                                        |
--                    |                                    |                                        |
--        ------------+-------------- ... -----------------+-------------             --------------+--------
--        |           |                                    |            |             |             |
--        |           |                                    |<--Front    |<---Sync     |<---Back     |
--        |           |                                    |    Porch-->|     Time--->|    Porch--->|
--  -------           |                                    |            ---------------             |
--                    |                                    |                                        |
--                    |<-------------------------------- Period ----------------------------------->|
--
-- horizontal timing signals
constant H_PIXELS: INTEGER:= H_SIZE;
constant H_FRONTPORCH:	INTEGER:= 56 + (800 - H_SIZE) / 2;
constant H_SYNCTIME: INTEGER:= 120;
constant H_BACKPORCH: INTEGER:= 63 + (800 - H_PIXELS) / 2;
constant H_PERIOD: INTEGER:= H_SYNCTIME + H_PIXELS + H_FRONTPORCH + H_BACKPORCH;

-- vertical timing signals
constant V_LINES: INTEGER:= V_SIZE;
constant V_FRONTPORCH: INTEGER:= 37 + (600 - V_SIZE) / 2;
constant V_SYNCTIME: INTEGER:= 6;
constant V_BACKPORCH: INTEGER:= 23 + (600 - V_SIZE) / 2;
constant V_PERIOD: INTEGER:= V_SYNCTIME + V_LINES + V_FRONTPORCH + V_BACKPORCH;

signal hcnt: std_logic_vector(10 downto 0);							-- horizontal pixel counter
signal vcnt: std_logic_vector(9 downto 0);							-- vertical line counter

begin

-- control the reset, increment and overflow of the horizontal pixel count
A: process(clock, reset)
begin
	-- reset asynchronously clears horizontal counter
	if reset = '0' then
		hcnt <= (others => '0');
	-- horiz. counter increments on rising edge of dot clock
	elsif (clock'event and clock = '1') then
		-- horiz. counter restarts after the horizontal period (set by the constants)
		if hcnt < H_PERIOD then
			hcnt <= hcnt + 1;
		else
			hcnt <= (others => '0');
		end if;
	end if;
end process;

-- control the reset, increment and overflow of the vertical line counter after every horizontal line
B: process(hsyncb, reset)
begin
	-- reset asynchronously clears line counter
	if reset='0' then
		vcnt <= (others => '0');
	-- vert. line counter increments after every horiz. line
	elsif (hsyncb'event and hsyncb = '1') then
		-- vert. line counter rolls-over after the set number of lines (set by the constants)
		if vcnt < V_PERIOD then
			vcnt <= vcnt + 1;
		else
			vcnt <= (others => '0');
		end if;
	end if;
end process;

-- set the horizontal sync high time and low time according to the constants
C: process(clock, reset)
begin
	-- reset asynchronously sets horizontal sync to inactive
	if reset = '0' then
		hsyncb <= '1';
	-- horizontal sync is recomputed on the rising edge of every dot clock
	elsif (clock'event and clock = '1') then
		-- horiz. sync is low in this interval to signal start of a new line
		if (hcnt >= (H_FRONTPORCH + H_PIXELS) and hcnt < (H_PIXELS + H_FRONTPORCH + H_SYNCTIME)) then
			hsyncb <= '0';
		else
			hsyncb <= '1';
		end if;
	end if;
end process;

-- set the vertical sync high time and low time according to the constants
D: process(hsyncb, reset)
begin
	-- reset asynchronously sets vertical sync to inactive
	if reset = '0' then
		vsyncb <= '1';
	-- vertical sync is recomputed at the end of every line of pixels
	elsif (hsyncb'event and hsyncb = '1') then
		-- vert. sync is low in this interval to signal start of a new frame
		if (vcnt >= (V_LINES + V_FRONTPORCH) and vcnt < (V_LINES + V_FRONTPORCH + V_SYNCTIME)) then
			vsyncb <= '0';
		else
			vsyncb <= '1';
		end if;
	end if;
end process;

-- whether it should latch the current data or not
-- (always with a 50MHz clock - blanking is handled on the RAMDAC by asserting a signal)
latch <= NOT reset;

-- asserts the blaking signal (active low)
E: process (clock)
begin
	if clock'EVENT and clock = '1' then
		-- if we are outside the visible range on the screen then tell the RAMDAC to blank
		-- in this section by putting enable low
		if hcnt >= H_PIXELS or vcnt >= V_LINES then
			enable <= '0';
		 else 
		 	enable <= '1';
		 end if;
	end if;
end process;

-- The video RAM address is built from the lower 9 bits of the vertical
-- line counter and bits 7-2 of the horizontal pixel counter.
-- Allows easy access for the current address of the current pixel in RAM
H:
hloc <= hcnt(9 downto 0);
vloc <= vcnt(9 downto 0);

end vgacore_arch;