hal_uart.s51

cc2430应用实例

        ORL	0xff,#0x40
//  425 
//  426 #if HAL_UART_0_ENABLE
//  427   // Set UART0 I/O location to P0.
//  428   PERCFG &= ~HAL_UART_0_PERCFG_BIT;
//  429 
//  430   /* Enable Tx and Rx on P0 */
//  431   P0SEL |= HAL_UART_0_P0_RX_TX;
//  432 
//  433   /* Make sure ADC doesnt use this */
//  434   ADCCFG &= ~HAL_UART_0_P0_RX_TX;
//  435 
//  436   /* Mode is UART Mode */
//  437   U0CSR = CSR_MODE;
//  438 
//  439   /* Flush it */
//  440   U0UCR = UCR_FLUSH;
//  441 #endif
//  442 
//  443 #if HAL_UART_1_ENABLE
//  444   // Set UART1 I/O location to P1.
//  445   PERCFG |= HAL_UART_1_PERCFG_BIT;
//  446 
//  447   /* Enable Tx and Rx on P1 */
//  448   P1SEL  |= HAL_UART_1_P1_RX_TX;
//  449 
//  450   /* Make sure ADC doesnt use this */
//  451   ADCCFG &= ~HAL_UART_1_P1_RX_TX;
//  452 
//  453   /* Mode is UART Mode */
//  454   U1CSR = CSR_MODE;
//  455 
//  456   /* Flush it */
//  457   U1UCR = UCR_FLUSH;
//  458 #endif
//  459 
//  460 #if HAL_UART_DMA
//  461   // Setup Tx by DMA.
//  462   ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_TX );
//  463 
//  464   // The start address of the destination.
//  465   HAL_DMA_SET_DEST( ch, DMA_UDBUF );
//  466 
//  467   // Using the length field to determine how many bytes to transfer.
//  468   HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN );
//  469 
//  470   // One byte is transferred each time.
//  471   HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_BYTE );
//  472 
//  473   // The bytes are transferred 1-by-1 on Tx Complete trigger.
//  474   HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE );
//  475   HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_TX );
//  476 
//  477   // The source address is decremented by 1 byte after each transfer.
//  478   HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_1 );
//  479 
//  480   // The destination address is constant - the Tx Data Buffer.
//  481   HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_0 );
//  482 
//  483   // The DMA is to be polled and shall not issue an IRQ upon completion.
//  484   HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE );
//  485 
//  486   // Xfer all 8 bits of a byte xfer.
//  487   HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS );
//  488 
//  489   // DMA Tx has shared priority for memory access - every other one.
//  490   HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH );
//  491 
//  492   // Setup Rx by DMA.
//  493   ch = HAL_DMA_GET_DESC1234( HAL_DMA_CH_RX );
//  494 
//  495   // The start address of the source.
//  496   HAL_DMA_SET_SOURCE( ch, DMA_UDBUF );
//  497 
//  498   // Using the length field to determine how many bytes to transfer.
//  499   HAL_DMA_SET_VLEN( ch, HAL_DMA_VLEN_USE_LEN );
//  500 
//  501   /* The trick is to cfg DMA to xfer 2 bytes for every 1 byte of Rx.
//  502    * The byte after the Rx Data Buffer is the Baud Cfg Register,
//  503    * which always has a known value. So init Rx buffer to inverse of that
//  504    * known value. DMA word xfer will flip the bytes, so every valid Rx byte
//  505    * in the Rx buffer will be preceded by a DMA_PAD char equal to the
//  506    * Baud Cfg Register value.
//  507    */
//  508   HAL_DMA_SET_WORD_SIZE( ch, HAL_DMA_WORDSIZE_WORD );
//  509 
//  510   // The bytes are transferred 1-by-1 on Rx Complete trigger.
//  511   HAL_DMA_SET_TRIG_MODE( ch, HAL_DMA_TMODE_SINGLE );
//  512   HAL_DMA_SET_TRIG_SRC( ch, DMATRIG_RX );
//  513 
//  514   // The source address is constant - the Rx Data Buffer.
//  515   HAL_DMA_SET_SRC_INC( ch, HAL_DMA_SRCINC_0 );
//  516 
//  517   // The destination address is incremented by 1 word after each transfer.
//  518   HAL_DMA_SET_DST_INC( ch, HAL_DMA_DSTINC_1 );
//  519 
//  520   // The DMA is to be polled and shall not issue an IRQ upon completion.
//  521   HAL_DMA_SET_IRQ( ch, HAL_DMA_IRQMASK_DISABLE );
//  522 
//  523   // Xfer all 8 bits of a byte xfer.
//  524   HAL_DMA_SET_M8( ch, HAL_DMA_M8_USE_8_BITS );
//  525 
//  526   // DMA has highest priority for memory access.
//  527   HAL_DMA_SET_PRIORITY( ch, HAL_DMA_PRI_HIGH );
//  528 #endif
//  529 }
        LJMP	?BRET
        CFI EndBlock cfiBlock0
//  530 
//  531 /******************************************************************************
//  532  * @fn      HalUARTOpen
//  533  *
//  534  * @brief   Open a port according tp the configuration specified by parameter.
//  535  *
//  536  * @param   port   - UART port
//  537  *          config - contains configuration information
//  538  *
//  539  * @return  Status of the function call
//  540  *****************************************************************************/

        RSEG BANKED_CODE:CODE:NOROOT(0)
//  541 uint8 HalUARTOpen( uint8 port, halUARTCfg_t *config )
HalUARTOpen:
        CFI Block cfiBlock1 Using cfiCommon0
        CFI Function HalUARTOpen
//  542 {
        FUNCALL HalUARTOpen, osal_mem_alloc
        LOCFRAME XSTACK, 12, STACK
        ARGFRAME XSTACK, 12, STACK
        FUNCALL HalUARTOpen, osal_mem_alloc
        LOCFRAME XSTACK, 12, STACK
        ARGFRAME XSTACK, 12, STACK
        MOV	A,#-0xc
        LCALL	?BANKED_ENTER_XDATA
        CFI DPH0 load(1, XDATA, add(CFA_XSP16, literal(-1)))
        CFI DPL0 load(1, XDATA, add(CFA_XSP16, literal(-2)))
        CFI ?BRET_EXT load(1, XDATA, add(CFA_XSP16, literal(-3)))
        CFI ?RET_HIGH load(1, XDATA, add(CFA_XSP16, literal(-4)))
        CFI ?RET_LOW load(1, XDATA, add(CFA_XSP16, literal(-5)))
        CFI R7 load(1, XDATA, add(CFA_XSP16, literal(-6)))
        CFI V3 load(1, XDATA, add(CFA_XSP16, literal(-7)))
        CFI V2 load(1, XDATA, add(CFA_XSP16, literal(-8)))
        CFI V1 load(1, XDATA, add(CFA_XSP16, literal(-9)))
        CFI V0 load(1, XDATA, add(CFA_XSP16, literal(-10)))
        CFI VB load(1, XDATA, add(CFA_XSP16, literal(-11)))
        CFI R6 load(1, XDATA, add(CFA_XSP16, literal(-12)))
        CFI CFA_SP SP+0
        CFI CFA_XSP16 add(XSP16, 12)
        ; Saved register size: 12
        ; Auto size: 0
        MOV	?V0 + 0,R2
        MOV	?V0 + 1,R3
//  543   uartCfg_t **cfgPP = NULL;
//  544   uartCfg_t *cfg;
//  545 
//  546 #if HAL_UART_0_ENABLE
//  547   if ( port == HAL_UART_PORT_0 )
//  548   {
//  549     cfgPP = &cfg0;
//  550   }
//  551 #endif
//  552 
//  553 #if HAL_UART_1_ENABLE
//  554   if ( port == HAL_UART_PORT_1 )
//  555   {
//  556     cfgPP = &cfg1;
//  557   }
//  558 #endif
//  559 
//  560   HAL_UART_ASSERT( cfgPP );
//  561 
//  562 #if HAL_UART_CLOSE
//  563   // Protect against user re-opening port before closing it.
//  564   HalUARTClose( port );
//  565 #else
//  566   HAL_UART_ASSERT( *cfgPP == NULL );
//  567 #endif
//  568 
//  569   HAL_UART_ASSERT( (config->baudRate == HAL_UART_BR_38400) ||
//  570                    (config->baudRate == HAL_UART_BR_115200) );
//  571 
//  572   /* Whereas runtime heap alloc can be expected to fail - one-shot system
//  573    * initialization must succeed, so no check for alloc fail.
//  574    */
//  575   *cfgPP = (uartCfg_t *)osal_mem_alloc( sizeof( uartCfg_t ) );
        ; Setup parameters for call to function osal_mem_alloc
        MOV	R2,#0x13
        MOV	R3,#0x0
        MOV	DPTR,#(osal_mem_alloc & 0xffff)
        MOV	A,#((osal_mem_alloc >> 16) & 0xff)
        LCALL	?BCALL               ; Banked call to: DPTR()
        MOV	DPTR,#0x0
        MOV	A,R2
        MOVX	@DPTR,A
        INC	DPTR
        MOV	A,R3
        MOVX	@DPTR,A
//  576   cfg = *cfgPP;
        MOV	DPTR,#0x0
        MOVX	A,@DPTR
        MOV	R6,A
        INC	DPTR
        MOVX	A,@DPTR
        MOV	R7,A
//  577   HAL_UART_ASSERT( cfg );
//  578 
//  579   cfg->rxMax = config->rx.maxBufSize;
        MOV	A,?V0 + 0
        ADD	A,#0xa
        MOV	?V0 + 2,A
        MOV	A,?V0 + 1
        ADDC	A,#0x0
        MOV	?V0 + 3,A
        MOV	DPL,?V0 + 2
        MOV	DPH,A
        MOVX	A,@DPTR
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        MOVX	@DPTR,A
//  580 
//  581 #if !HAL_UART_BIG_TX_BUF
//  582   HAL_UART_ASSERT( (config->tx.maxBufSize < 256) );
//  583 #endif
//  584   cfg->txMax = config->tx.maxBufSize;
        MOV	A,R6
        ADD	A,#0xc
        MOV	R0,A
        MOV	A,R7
        ADDC	A,#0x0
        MOV	R1,A
        MOV	A,?V0 + 0
        ADD	A,#0x12
        MOV	DPL,A
        MOV	A,?V0 + 1
        ADDC	A,#0x0
        MOV	DPH,A
        MOVX	A,@DPTR
        MOV	DPL,R0
        MOV	DPH,R1
        MOVX	@DPTR,A
//  585   cfg->txBuf = osal_mem_alloc( cfg->txMax+1 );
        ; Setup parameters for call to function osal_mem_alloc
        MOV	R0,A
        MOV	A,#0x1
        ADD	A,R0
        MOV	R2,A
        CLR	A
        ADDC	A,#0x0
        MOV	R3,A
        MOV	DPTR,#(osal_mem_alloc & 0xffff)
        MOV	A,#((osal_mem_alloc >> 16) & 0xff)
        LCALL	?BCALL               ; Banked call to: DPTR()
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        MOV	A,R2
        MOVX	@DPTR,A
        INC	DPTR
        MOV	A,R3
        MOVX	@DPTR,A
//  586 
//  587   cfg->rxHead = cfg->rxTail = 0;
        CLR	A
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        INC	DPTR
        MOVX	@DPTR,A
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        MOVX	@DPTR,A
//  588   cfg->txHead = cfg->txTail = 0;
        MOV	A,R6
        ADD	A,#0xb
        MOV	DPL,A
        MOV	A,R7
        ADDC	A,#0x0
        MOV	DPH,A
        CLR	A
        MOVX	@DPTR,A
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        MOVX	@DPTR,A
//  589   cfg->rxHigh = config->rx.maxBufSize - config->flowControlThreshold;
        MOV	DPL,?V0 + 0
        MOV	DPH,?V0 + 1
        INC	DPTR
        INC	DPTR
        INC	DPTR
        MOVX	A,@DPTR
        MOV	R0,A
        MOV	DPL,?V0 + 2
        MOV	DPH,?V0 + 3
        MOVX	A,@DPTR
        CLR	C
        SUBB	A,R0
        MOV	DPL,R6
        MOV	DPH,R7
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        INC	DPTR
        MOVX	@DPTR,A
//  590   cfg->rxCB = config->callBackFunc;
        MOV	A,?V0 + 0
        ADD	A,#0x1b
        MOV	DPL,A
        MOV	A,?V0 + 1
        ADDC	A,#0x0
        MOV	DPH,A
        MOVX	A,@DPTR
        MOV	R1,A
        INC	DPTR
        MOVX	A,@DPTR
        MOV	R2,A
        INC	DPTR
        MOVX	A,@DPTR
        MOV	R3,A
        MOV	A,R6
        ADD	A,#0x10
        MOV	DPL,A
        MOV	A,R7
        ADDC	A,#0x0
        MOV	DPH,A
        MOV	A,R1
        MOVX	@DPTR,A
        INC	DPTR
        MOV	A,R2
        MOVX	@DPTR,A
        INC	DPTR
        MOV	A,R3
        MOVX	@DPTR,A
//  591 
//  592 #if HAL_UART_0_ENABLE
//  593   if ( port == HAL_UART_PORT_0 )
//  594   {
//  595     // Only supporting 38400 or 115200 for code size - other is possible.
//  596     U0BAUD = (config->baudRate == HAL_UART_BR_38400) ? 59 : 216;
//  597     U0GCR = (config->baudRate == HAL_UART_BR_38400) ? 10 : 11;
//  598 
//  599     U0CSR |= CSR_RE;
//  600 
//  601 #if HAL_UART_DMA == 1
//  602     cfg->flag = UART_CFG_DMA;
//  603     HAL_UART_ASSERT( (config->rx.maxBufSize <= 128) );
//  604     HAL_UART_ASSERT( (config->rx.maxBufSize > SAFE_RX_MIN) );
//  605     cfg->rxBuf = osal_mem_alloc( cfg->rxMax*2 );
//  606     osal_memset( cfg->rxBuf, ~DMA_PAD, cfg->rxMax*2 );
//  607     DMA_RX( cfg );
//  608 #else
//  609     cfg->flag = 0;
//  610     HAL_UART_ASSERT( (config->rx.maxBufSize < 256) );