hal_adc.s51

cc2430应用实例

//  182   }
//  183 
//  184   /* Enable channel */
//  185   ADCCFG |= adcChannel;
??HalAdcRead_0:
        MOV	A,R4
        ORL	A,0xf2
        MOV	0xf2,A
//  186 
//  187   /* Convert resolution to decimation rate */
//  188   switch (resolution)
        MOV	A,R2
        LCALL	?UC_SWITCH_DENSE
`?<Jumptable for HalAdcRead>_0`:
        DB        1
        DB        2
        DW        ??HalAdcRead_3
        DW        ??HalAdcRead_4
        DW        ??HalAdcRead_5
        DW        ??HalAdcRead_6
//  189   {
//  190     case HAL_ADC_RESOLUTION_8:
//  191       resbits = HAL_ADC_DEC_064;
??HalAdcRead_4:
        MOV	R3,#0x0
        SJMP	??HalAdcRead_7
//  192       break;
//  193     case HAL_ADC_RESOLUTION_10:
//  194       resbits = HAL_ADC_DEC_128;
??HalAdcRead_5:
        MOV	R3,#0x10
        SJMP	??HalAdcRead_7
//  195       break;
//  196     case HAL_ADC_RESOLUTION_12:
//  197       resbits = HAL_ADC_DEC_256;
??HalAdcRead_6:
        MOV	R3,#0x20
        SJMP	??HalAdcRead_7
//  198       break;
//  199     case HAL_ADC_RESOLUTION_14:
//  200     default:
//  201       resbits = HAL_ADC_DEC_512;
??HalAdcRead_3:
        MOV	R3,#0x30
//  202       break;
//  203   }
//  204 
//  205   /* read ADCL,ADCH to clear EOC */
//  206   tmp = ADCL;
??HalAdcRead_7:
        MOV	A,0xba
        MOV	DPL,?XSP + 0
        MOV	DPH,?XSP + 1
        MOVX	@DPTR,A
//  207   tmp = ADCH;
        MOV	A,0xbb
        MOVX	@DPTR,A
//  208 
//  209   /* Setup Sample */
//  210   adctemp = ADCCON3;
        MOV	A,0xb6
//  211   adctemp &= ~(HAL_ADC_CHN_BITS | HAL_ADC_DEC_BITS | HAL_ADC_REF_BITS);
//  212   adctemp |= channel | resbits | HAL_ADC_REF_VOLT;
//  213 
//  214   /* writing to this register starts the extra conversion */
//  215   ADCCON3 = adctemp;
        MOV	A,R3
        ORL	A,R1
        ORL	A,#0x80
        MOV	0xb6,A
//  216 
//  217   /* Wait for the conversion to be done */
//  218   while (!(ADCCON1 & HAL_ADC_EOC));
??HalAdcRead_8:
        MOV	A,0xb4
        MOV	C,0xE0 /* A   */.7
        JNC	??HalAdcRead_8
//  219 
//  220   /* Disable channel after done conversion */
//  221   ADCCFG &= ~adcChannel;
        MOV	A,R4
        CPL	A
        ANL	A,0xf2
        MOV	0xf2,A
//  222 
//  223   /* Read the result */
//  224   reading = (int16) (ADCL);
        MOV	R3,0xba
        MOV	DPL,R3
        MOV	R0,DPL
//  225   reading |= (int16) (ADCH << 8);
        MOV	A,0xbb
        MOV	R1,A
//  226 
//  227   /* Treat small negative as 0 */
//  228   if (reading < 0)
        CLR	C
        MOV	A,R0
        SUBB	A,#0x0
        MOV	A,R1
        SUBB	A,#0x0
        MOV	C,0xD0 /* PSW */.2
        XRL	A,PSW
        RLC	A
        JNC	??HalAdcRead_9
//  229     reading = 0;
        MOV	R0,#0x0
        MOV	R1,#0x0
//  230 
//  231   switch (resolution)
??HalAdcRead_9:
        MOV	A,R2
        LCALL	?UC_SWITCH_DENSE
`?<Jumptable for HalAdcRead>_1`:
        DB        1
        DB        2
        DW        ??HalAdcRead_10
        DW        ??HalAdcRead_11
        DW        ??HalAdcRead_12
        DW        ??HalAdcRead_13
//  232   {
//  233     case HAL_ADC_RESOLUTION_8:
//  234       reading >>= 8;
??HalAdcRead_11:
        MOV	?V0 + 0,R0
        MOV	?V0 + 1,R1
        MOV	A,#0x8
        SJMP	??HalAdcRead_14
//  235       break;
//  236     case HAL_ADC_RESOLUTION_10:
//  237       reading >>= 6;
??HalAdcRead_12:
        MOV	?V0 + 0,R0
        MOV	?V0 + 1,R1
        MOV	A,#0x6
        SJMP	??HalAdcRead_14
//  238       break;
//  239     case HAL_ADC_RESOLUTION_12:
//  240       reading >>= 4;
??HalAdcRead_13:
        MOV	?V0 + 0,R0
        MOV	?V0 + 1,R1
        MOV	A,#0x4
??HalAdcRead_14:
        MOV	R0,#?V0 + 0
        LCALL	?SS_SHR
        MOV	R0,?V0 + 0
        MOV	R1,?V0 + 1
//  241       break;
//  242     case HAL_ADC_RESOLUTION_14:
//  243     default:
//  244     break;
//  245   }
//  246 #endif
//  247 
//  248   return ((uint16)reading);
??HalAdcRead_10:
        MOV	A,R0
        MOV	R2,A
        MOV	A,R1
        MOV	R3,A
        MOV	A,#0x1
        LCALL	?DEALLOC_XSTACK8
        CFI CFA_XSP16 add(XSP16, 10)
        MOV	R7,#0x2
        LJMP	?BANKED_LEAVE_XDATA
        CFI EndBlock cfiBlock2
//  249 }
//  250 
//  251 /**************************************************************************************************
//  252  * @fn      HalAdcCheckVdd
//  253  *
//  254  * @brief   Check the Vdd and return TRUE if it greater than or equal the limit
//  255  *
//  256  * @param   limit - limit that needs to be checked with the Vdd
//  257  *
//  258  * @return  TRUE if Vdd >= limit, FALSE otherwise
//  259  *
//  260  **************************************************************************************************/

        RSEG BANKED_CODE:CODE:NOROOT(0)
//  261 bool HalAdcCheckVdd (uint8 limit)
HalAdcCheckVdd:
        CFI Block cfiBlock3 Using cfiCommon0
        CFI Function HalAdcCheckVdd
//  262 {
        PUSH	DPL
        CFI DPL0 Frame(CFA_SP, 4)
        CFI CFA_SP SP+-4
        PUSH	DPH
        CFI DPH0 Frame(CFA_SP, 5)
        CFI CFA_SP SP+-5
        ; Saved register size: 2
        ; Auto size: 0
//  263   uint16 value;
//  264 
//  265   /* If rev C or earlier, dont check the voltage */
//  266   if (CHVER < REV_D)
        MOV	DPTR,#-0x20a0
        MOVX	A,@DPTR
        CLR	C
        SUBB	A,#0x3
        JNC	??HalAdcCheckVdd_0
//  267   {
//  268     return TRUE;
??HalAdcCheckVdd_1:
        MOV	R1,#0x1
        SJMP	??HalAdcCheckVdd_2
//  269   }
//  270 
//  271   /* Clear ADC interrupt flag */
//  272   ADCIF = 0;
??HalAdcCheckVdd_0:
        CLR	0x88.5
//  273 
//  274   /* Setup the new value for conversion */
//  275   ADCCON3 = (HAL_ADC_REF_125V | HAL_ADC_DEC_064 | HAL_ADC_CHN_VDD3);
        MOV	0xb6,#0xf
//  276 
//  277   /* Wait for the conversion to finish */
//  278   while ( !ADCIF );
??HalAdcCheckVdd_3:
        MOV	C,0x88.5
        JNC	??HalAdcCheckVdd_3
//  279 
//  280   /* Get the result */
//  281   value = ADCL;
        MOV	R2,0xba
//  282   value |= ((uint16) ADCH) << 8;
        MOV	A,0xbb
        MOV	R3,A
//  283 
//  284   /* Check the limit and return */
//  285   return ( value >= HalAdcVddLimit[limit] );
        MOV	A,R1
        CLR	C
        RLC	A
        MOV	R0,A
        CLR	A
        RLC	A
        MOV	R1,A
        MOV	A,R0
        ADD	A,#(??HalAdcVddLimit & 0xff)
        MOV	DPL,A
        MOV	A,R1
        ADDC	A,#((??HalAdcVddLimit >> 8) & 0xff)
        MOV	DPH,A
        CLR	A
        MOVC	A,@A+DPTR
        MOV	R0,A
        MOV	A,#0x1
        MOVC	A,@A+DPTR
        MOV	R1,A
        CLR	C
        MOV	A,R2
        SUBB	A,R0
        MOV	A,R3
        SUBB	A,R1
        JNC	??HalAdcCheckVdd_1
        MOV	R1,#0x0
??HalAdcCheckVdd_2:
        LJMP	?Subroutine0 & 0xFFFF
        CFI EndBlock cfiBlock3
//  286 }

        ASEGN SFR_AN:DATA:NOROOT,088H
// union <unnamed> volatile __sfr _A_TCON
_A_TCON:
        DS 1

        END
//  287 
//  288 /**************************************************************************************************
//  289 **************************************************************************************************/
//  290 
//  291 
//  292 
//  293 
// 
// 319 bytes in segment BANKED_CODE
//  18 bytes in segment CODE_C
//   7 bytes in segment SFR_AN
// 
// 337 bytes of CODE memory
//   0 bytes of DATA memory (+ 7 bytes shared)
//
//Errors: none
//Warnings: none