📄 mac_mcu.lst
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189 T2IE = 1;
\ 000064 D2BA SETB 0xb8.2
190
191 /* configure clock to use XOSC */
192 SLEEP &= ~OSC_PD; /* turn on 16MHz RC and 32MHz XOSC */
\ 000066 53BEFB ANL 0xbe,#0xfb
193 while (!(SLEEP & XOSC_STB)); /* wait for 32MHz XOSC stable */
\ ??macMcuInit_2:
\ 000069 E5BE MOV A,0xbe
\ 00006B A2E6 MOV C,0xE0 /* A */.6
\ 00006D 50FA JNC ??macMcuInit_2
194 asm("NOP"); /* chip bug workaround */
\ 00006F 00 NOP
195 for (i=0; i<504; i++) asm("NOP"); /* Require 63us delay for Rev B */
\ 000070 78F8 MOV R0,#-0x8
\ 000072 7901 MOV R1,#0x1
\ ??macMcuInit_3:
\ 000074 00 NOP
\ 000075 E8 MOV A,R0
\ 000076 24FF ADD A,#-0x1
\ 000078 18 DEC R0
\ 000079 E9 MOV A,R1
\ 00007A 34FF ADDC A,#-0x1
\ 00007C F9 MOV R1,A
\ 00007D E8 MOV A,R0
\ 00007E 7001 JNZ ??macMcuInit_4
\ 000080 E9 MOV A,R1
\ ??macMcuInit_4:
\ 000081 70F1 JNZ ??macMcuInit_3
196 CLKCON = (0x00 | OSC_32KHZ); /* 32MHz XOSC */
\ 000083 75C600 MOV 0xc6,#0x0
197 while (CLKCON != (0x00 | OSC_32KHZ));
\ ??macMcuInit_5:
\ 000086 E5C6 MOV A,0xc6
\ 000088 70FC JNZ ??macMcuInit_5
198 SLEEP |= OSC_PD; /* turn off 16MHz RC */
\ 00008A 43BE04 ORL 0xbe,#0x4
199
200
201 /*----------------------------------------------------------------------------------------------
202 * Initialize random seed value.
203 */
204
205 /* turn on radio power */
206 RFPWR &= ~RREG_RADIO_PD;
\ 00008D 90DF17 MOV DPTR,#-0x20e9
\ 000090 E0 MOVX A,@DPTR
\ 000091 C2E3 CLR 0xE0 /* A */.3
\ 000093 F0 MOVX @DPTR,A
207 while((RFPWR & ADI_RADIO_PD));
\ ??macMcuInit_6:
\ 000094 E0 MOVX A,@DPTR
\ 000095 A2E4 MOV C,0xE0 /* A */.4
\ 000097 40FB JC ??macMcuInit_6
208
209 /*
210 * Set radio for infinite reception. Once radio reaches this state,
211 * it will stay in receive mode regardless RF activity.
212 */
213 MDMCTRL1L = MDMCTRL1L_RESET_VALUE | RX_MODE_INFINITE_RECEPTION;
\ 000099 7402 MOV A,#0x2
\ 00009B 90DF05 MOV DPTR,#-0x20fb
\ 00009E F0 MOVX @DPTR,A
214
215 /* turn on the receiver */
216 macRxOn();
\ 00009F ; Setup parameters for call to function macRxOn
\ 00009F 90.... MOV DPTR,#(macRxOn & 0xffff)
\ 0000A2 74.. MOV A,#((macRxOn >> 16) & 0xff)
\ 0000A4 12.... LCALL ?BCALL ; Banked call to: DPTR()
\ 0000A7 802C SJMP ??macMcuInit_7
217
218 /*
219 * Wait for radio to reach infinite reception state. Once it does,
220 * The least significant bit of ADTSTH should be pretty random.
221 */
222 while (FSMSTATE != FSM_FFCTRL_STATE_RX_INF)
223
224 /* put 16 random bits into the seed value */
225 {
226 uint16 rndSeed;
227 uint8 i;
228
229 rndSeed = 0;
\ ??macMcuInit_8:
\ 0000A9 7800 MOV R0,#0x0
\ 0000AB 7900 MOV R1,#0x0
230
231 for(i=0; i<16; i++)
\ 0000AD 7C10 MOV R4,#0x10
232 {
233 /* use most random bit of analog to digital receive conversion to populate the random seed */
234 rndSeed = (rndSeed << 1) | (ADCTSTH & 0x01);
\ ??macMcuInit_9:
\ 0000AF E8 MOV A,R0
\ 0000B0 C3 CLR C
\ 0000B1 33 RLC A
\ 0000B2 F8 MOV R0,A
\ 0000B3 E9 MOV A,R1
\ 0000B4 33 RLC A
\ 0000B5 F9 MOV R1,A
\ 0000B6 90DF3A MOV DPTR,#-0x20c6
\ 0000B9 E0 MOVX A,@DPTR
\ 0000BA A2E0 MOV C,0xE0 /* A */.0
\ 0000BC E4 CLR A
\ 0000BD 92E0 MOV 0xE0 /* A */.0,C
\ 0000BF 48 ORL A,R0
\ 0000C0 F8 MOV R0,A
235 }
\ 0000C1 1C DEC R4
\ 0000C2 EC MOV A,R4
\ 0000C3 70EA JNZ ??macMcuInit_9
236
237 /*
238 * The seed value must not be zero. If it is, the psuedo random sequence will be always be zero.
239 * There is an extremely small chance this seed could randomly be zero (more likely some type of
240 * hardware problem would cause this). The following check makes sure this does not happen.
241 */
242 if (rndSeed == 0x0000)
\ 0000C5 E8 MOV A,R0
\ 0000C6 7001 JNZ ??macMcuInit_10
\ 0000C8 E9 MOV A,R1
\ ??macMcuInit_10:
\ 0000C9 7004 JNZ ??macMcuInit_11
243 {
244 rndSeed = 0xBEEF; /* completely arbitrary "random" value */
\ 0000CB 78EF MOV R0,#-0x11
\ 0000CD 79BE MOV R1,#-0x42
245 }
246
247 /*
248 * Two writes to RNDL will set the random seed. A write to RNDL copies current contents
249 * of RNDL to RNDH before writing new the value to RNDL.
250 */
251 RNDL = rndSeed & 0xFF;
\ ??macMcuInit_11:
\ 0000CF E8 MOV A,R0
\ 0000D0 F5BC MOV 0xbc,A
252 RNDL = rndSeed >> 8;
\ 0000D2 E9 MOV A,R1
\ 0000D3 F5BC MOV 0xbc,A
253 }
\ ??macMcuInit_7:
\ 0000D5 90DF39 MOV DPTR,#-0x20c7
\ 0000D8 E0 MOVX A,@DPTR
\ 0000D9 641F XRL A,#0x1f
\ 0000DB 70CC JNZ ??macMcuInit_8
254
255 /* turn off the receiver */
256 macRxOff();
\ 0000DD ; Setup parameters for call to function macRxOff
\ 0000DD 90.... MOV DPTR,#(macRxOff & 0xffff)
\ 0000E0 74.. MOV A,#((macRxOff >> 16) & 0xff)
\ 0000E2 12.... LCALL ?BCALL ; Banked call to: DPTR()
257
258 /* take receiver out of infinite reception mode; set back to normal operation */
259 MDMCTRL1L = MDMCTRL1L_RESET_VALUE | RX_MODE_NORMAL_OPERATION;
\ 0000E5 E4 CLR A
\ 0000E6 90DF05 MOV DPTR,#-0x20fb
\ 0000E9 F0 MOVX @DPTR,A
260
261 /* turn radio back off */
262 RFPWR |= RREG_RADIO_PD;
\ 0000EA 90DF17 MOV DPTR,#-0x20e9
\ 0000ED E0 MOVX A,@DPTR
\ 0000EE D2E3 SETB 0xE0 /* A */.3
\ 0000F0 F0 MOVX @DPTR,A
263 }
\ 0000F1 02.... LJMP ?Subroutine3 & 0xFFFF
\ In segment BANKED_CODE, align 1, keep-with-next
\ ?Subroutine3:
\ 000000 D083 POP DPH
\ 000002 D082 POP DPL
\ 000004 02.... LJMP ?BRET
264
265
266 /**************************************************************************************************
267 * @fn macMcuRandomByte
268 *
269 * @brief Returns a random byte using a special hardware feature that generates new
270 * random values based on the truly random seed set earlier.
271 *
272 * @param none
273 *
274 * @return a random byte
275 **************************************************************************************************
276 */
\ In segment BANKED_CODE, align 1, keep-with-next
277 uint8 macMcuRandomByte(void)
\ macMcuRandomByte:
278 {
\ 000000 ; Saved register size: 0
\ 000000 ; Auto size: 0
279 /* clock the random generator to get a new random value */
280 ADCCON1 = (ADCCON1 & ~RCTRL_BITS) | RCTRL_CLOCK_LFSR;
\ 000000 74F3 MOV A,#-0xd
\ 000002 55B4 ANL A,0xb4
\ 000004 4404 ORL A,#0x4
\ 000006 F5B4 MOV 0xb4,A
281
282 /* return new randomized value from hardware */
283 return(RNDH);
\ 000008 A9BD MOV R1,0xbd
\ 00000A 02.... LJMP ?BRET
284 }
285
286
287 /**************************************************************************************************
288 * @fn macMcuTimerCount
289 *
290 * @brief Returns the upper eight bits of hardware timer count. The full 16-bit timer
291 * count is not returned because the timer compare feature only compares one byte.
292 *
293 * @param none
294 *
295 * @return upper eight bits of hardware timer count
296 **************************************************************************************************
297 */
\ In segment BANKED_CODE, align 1, keep-with-next
298 uint8 macMcuTimerCount(void)
\ macMcuTimerCount:
299 {
\ 000000 C082 PUSH DPL
\ 000002 C083 PUSH DPH
\ 000004 ; Saved register size: 2
\ 000004 ; Auto size: 1
\ 000004 74FF MOV A,#-0x1
\ 000006 12.... LCALL ?ALLOC_XSTACK8
300 uint8 volatile temp;
301
302 /* reading T2TLD latches T2THD */
303 temp = T2TLD;
\ 000009 E5A6 MOV A,0xa6
\ 00000B 85..82 MOV DPL,?XSP + 0
\ 00000E 85..83 MOV DPH,?XSP + 1
\ 000011 F0 MOVX @DPTR,A
304 return(T2THD);
\ 000012 A9A7 MOV R1,0xa7
\ 000014 7401 MOV A,#0x1
\ 000016 12.... LCALL ?DEALLOC_XSTACK8
\ 000019 02.... LJMP ?Subroutine3 & 0xFFFF
305 }
306
307
308 /**************************************************************************************************
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