uart.map.eqn

一个完整的用cpld实现串口功能的代码。经过验证

--operation mode is normal

A1L742 = state_tras[2] & (!state_tras[0] # !state_tras[1]) # !state_tras[2] & state_tras[1];


--A1L731 is Mux~3243
--operation mode is normal

A1L731 = A1L841 & A1L742 # !A1L841 & (trasstart & !A1L231);


--A1L831 is Mux~3245
--operation mode is normal

A1L831 = state_tras[1] & (!state_tras[3]) # !state_tras[1] & (state_tras[2] & (!state_tras[3]) # !state_tras[2] & (state_tras[0] # state_tras[3]));


--A1L042 is trasstart~39
--operation mode is normal

A1L042 = key_entry2 & (!A1L831);


--A1L612 is send_state[2]~116
--operation mode is normal

A1L612 = key_entry2 & state_tras[0] & state_tras[2] & A1L512;


--A1L712 is send_state[2]~117
--operation mode is normal

A1L712 = A1L841 & send_state[0] & send_state[1] & A1L612;


--A1L312 is send_state[1]~118
--operation mode is normal

A1L312 = A1L841 & send_state[0] & A1L612;


--A1L931 is Mux~3249
--operation mode is normal

A1L931 = state_tras[0] & state_tras[2] & state_tras[1];


--div_reg[15] is div_reg[15]
--operation mode is normal

div_reg[15]_lut_out = A1L3;
div_reg[15] = DFFEAS(div_reg[15]_lut_out, clk, rst, , , , , , );


--div_reg[14] is div_reg[14]
--operation mode is normal

div_reg[14]_lut_out = A1L4;
div_reg[14] = DFFEAS(div_reg[14]_lut_out, clk, rst, , , , , , );


--div_reg[13] is div_reg[13]
--operation mode is normal

div_reg[13]_lut_out = A1L6;
div_reg[13] = DFFEAS(div_reg[13]_lut_out, clk, rst, , , , , , );


--div_reg[12] is div_reg[12]
--operation mode is normal

div_reg[12]_lut_out = A1L8;
div_reg[12] = DFFEAS(div_reg[12]_lut_out, clk, rst, , , , , , );


--A1L941 is reduce_nor~228
--operation mode is normal

A1L941 = div_reg[15] # div_reg[14] # div_reg[13] # div_reg[12];


--div_reg[11] is div_reg[11]
--operation mode is normal

div_reg[11]_lut_out = A1L01;
div_reg[11] = DFFEAS(div_reg[11]_lut_out, clk, rst, , , , , , );


--div_reg[10] is div_reg[10]
--operation mode is normal

div_reg[10]_lut_out = A1L21;
div_reg[10] = DFFEAS(div_reg[10]_lut_out, clk, rst, , , , , , );


--div_reg[9] is div_reg[9]
--operation mode is normal

div_reg[9]_lut_out = A1L41;
div_reg[9] = DFFEAS(div_reg[9]_lut_out, clk, rst, , , , , , );


--div_reg[8] is div_reg[8]
--operation mode is normal

div_reg[8]_lut_out = A1L61 & !A1L351;
div_reg[8] = DFFEAS(div_reg[8]_lut_out, clk, rst, , , , , , );


--A1L051 is reduce_nor~229
--operation mode is normal

A1L051 = div_reg[11] # div_reg[10] # div_reg[9] # !div_reg[8];


--div_reg[7] is div_reg[7]
--operation mode is normal

div_reg[7]_lut_out = A1L81;
div_reg[7] = DFFEAS(div_reg[7]_lut_out, clk, rst, , , , , , );


--div_reg[6] is div_reg[6]
--operation mode is normal

div_reg[6]_lut_out = A1L02;
div_reg[6] = DFFEAS(div_reg[6]_lut_out, clk, rst, , , , , , );


--div_reg[5] is div_reg[5]
--operation mode is normal

div_reg[5]_lut_out = A1L22;
div_reg[5] = DFFEAS(div_reg[5]_lut_out, clk, rst, , , , , , );


--div_reg[4] is div_reg[4]
--operation mode is normal

div_reg[4]_lut_out = A1L42;
div_reg[4] = DFFEAS(div_reg[4]_lut_out, clk, rst, , , , , , );


--A1L151 is reduce_nor~230
--operation mode is normal

A1L151 = div_reg[7] # div_reg[6] # div_reg[5] # div_reg[4];


--div_reg[3] is div_reg[3]
--operation mode is normal

div_reg[3]_lut_out = A1L62;
div_reg[3] = DFFEAS(div_reg[3]_lut_out, clk, rst, , , , , , );


--div_reg[2] is div_reg[2]
--operation mode is normal

div_reg[2]_lut_out = A1L82 & !A1L351;
div_reg[2] = DFFEAS(div_reg[2]_lut_out, clk, rst, , , , , , );


--div_reg[1] is div_reg[1]
--operation mode is normal

div_reg[1]_lut_out = A1L03;
div_reg[1] = DFFEAS(div_reg[1]_lut_out, clk, rst, , , , , , );


--div_reg[0] is div_reg[0]
--operation mode is normal

div_reg[0]_lut_out = A1L23;
div_reg[0] = DFFEAS(div_reg[0]_lut_out, clk, rst, , , , , , );


--A1L251 is reduce_nor~231
--operation mode is normal

A1L251 = div_reg[3] # div_reg[2] # !div_reg[0] # !div_reg[1];


--A1L351 is reduce_nor~232
--operation mode is normal

A1L351 = !A1L941 & !A1L051 & !A1L151 & !A1L251;


--A1L821 is key_entry2~71
--operation mode is normal

A1L821 = !A1L531 # !send_state[1] # !send_state[2] # !send_state[0];


--rxd_reg1 is rxd_reg1
--operation mode is normal

rxd_reg1_lut_out = rxd;
rxd_reg1 = DFFEAS(rxd_reg1_lut_out, clkbaud8x, rst, , , , , , );


--recstart is recstart
--operation mode is normal

recstart_lut_out = A1L741;
recstart = DFFEAS(recstart_lut_out, clkbaud8x, rst, , A1L541, , , , );


--A1L101 is div8_rec_reg[2]~51
--operation mode is normal

A1L101 = div8_rec_reg[1] & div8_rec_reg[0] & recstart;


--A1L99 is div8_rec_reg[1]~52
--operation mode is normal

A1L99 = div8_rec_reg[0] & recstart;


--A1L822 is state_rec[0]~802
--operation mode is normal

A1L822 = state_rec[3] & (state_rec[2] # state_rec[1]) # !state_rec[3] & !state_rec[2] & !state_rec[1] & !state_rec[0];


--A1L741 is reduce_nor~5
--operation mode is normal

A1L741 = !state_rec[3] & !state_rec[0] & !state_rec[2] & !state_rec[1];


--recstart_tmp is recstart_tmp
--operation mode is normal

recstart_tmp_lut_out = rxd_reg2 & (!recstart_tmp & !rxd_reg1);
recstart_tmp = DFFEAS(recstart_tmp_lut_out, clkbaud8x, rst, , A1L741, , , , );


--A1L922 is state_rec[0]~803
--operation mode is normal

A1L922 = A1L741 & (!recstart_tmp) # !A1L741 & (A1L822 # !A1L791);


--A1L1 is add~898
--operation mode is normal

A1L1 = state_rec[0] & state_rec[1];


--A1L332 is state_rec~804
--operation mode is normal

A1L332 = state_rec[3] & (state_rec[0] # state_rec[2] # state_rec[1]);


--A1L2 is add~899
--operation mode is normal

A1L2 = state_rec[0] & state_rec[2] & state_rec[1];


--A1L752 is txd_buf~1747
--operation mode is normal

A1L752 = send_state[1] & state_tras[1] & (!send_state[2]);


--txd_buf[2] is txd_buf[2]
--operation mode is normal

txd_buf[2]_lut_out = A1L952 # txd_buf[3] & !state_tras[3] # !key_entry2;
txd_buf[2] = DFFEAS(txd_buf[2]_lut_out, clkbaud8x, rst, , A1L642, , , , );


--A1L942 is txd_buf[1]~1748
--operation mode is normal

A1L942 = !state_tras[1] & (state_tras[2] # !state_tras[0]) # !state_tras[3];


--cnt_delay[18] is cnt_delay[18]
--operation mode is normal

cnt_delay[18]_lut_out = A1L43 & A1L641;
cnt_delay[18] = DFFEAS(cnt_delay[18]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[13] is cnt_delay[13]
--operation mode is normal

cnt_delay[13]_lut_out = A1L63 & A1L641;
cnt_delay[13] = DFFEAS(cnt_delay[13]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[12] is cnt_delay[12]
--operation mode is normal

cnt_delay[12]_lut_out = A1L83 & A1L641;
cnt_delay[12] = DFFEAS(cnt_delay[12]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[10] is cnt_delay[10]
--operation mode is normal

cnt_delay[10]_lut_out = A1L04 & A1L641;
cnt_delay[10] = DFFEAS(cnt_delay[10]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L451 is reduce_nor~233
--operation mode is normal

A1L451 = !cnt_delay[10] # !cnt_delay[12] # !cnt_delay[13] # !cnt_delay[18];


--cnt_delay[17] is cnt_delay[17]
--operation mode is normal

cnt_delay[17]_lut_out = A1L24;
cnt_delay[17] = DFFEAS(cnt_delay[17]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[16] is cnt_delay[16]
--operation mode is normal

cnt_delay[16]_lut_out = A1L44;
cnt_delay[16] = DFFEAS(cnt_delay[16]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[15] is cnt_delay[15]
--operation mode is normal

cnt_delay[15]_lut_out = A1L64;
cnt_delay[15] = DFFEAS(cnt_delay[15]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[14] is cnt_delay[14]
--operation mode is normal

cnt_delay[14]_lut_out = A1L84;
cnt_delay[14] = DFFEAS(cnt_delay[14]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L912 is start_delaycnt~220
--operation mode is normal

A1L912 = !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14];


--cnt_delay[11] is cnt_delay[11]
--operation mode is normal

cnt_delay[11]_lut_out = A1L05;
cnt_delay[11] = DFFEAS(cnt_delay[11]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[9] is cnt_delay[9]
--operation mode is normal

cnt_delay[9]_lut_out = A1L25;
cnt_delay[9] = DFFEAS(cnt_delay[9]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[7] is cnt_delay[7]
--operation mode is normal

cnt_delay[7]_lut_out = A1L45;
cnt_delay[7] = DFFEAS(cnt_delay[7]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[6] is cnt_delay[6]
--operation mode is normal

cnt_delay[6]_lut_out = A1L65;
cnt_delay[6] = DFFEAS(cnt_delay[6]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L022 is start_delaycnt~221
--operation mode is normal

A1L022 = !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6];


--cnt_delay[5] is cnt_delay[5]
--operation mode is normal

cnt_delay[5]_lut_out = A1L85;
cnt_delay[5] = DFFEAS(cnt_delay[5]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[4] is cnt_delay[4]
--operation mode is normal

cnt_delay[4]_lut_out = A1L06;
cnt_delay[4] = DFFEAS(cnt_delay[4]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[3] is cnt_delay[3]
--operation mode is normal

cnt_delay[3]_lut_out = A1L26;
cnt_delay[3] = DFFEAS(cnt_delay[3]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[2] is cnt_delay[2]
--operation mode is normal

cnt_delay[2]_lut_out = A1L46;
cnt_delay[2] = DFFEAS(cnt_delay[2]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L122 is start_delaycnt~222
--operation mode is normal

A1L122 = !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2];


--cnt_delay[1] is cnt_delay[1]
--operation mode is normal

cnt_delay[1]_lut_out = A1L66;
cnt_delay[1] = DFFEAS(cnt_delay[1]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[0] is cnt_delay[0]
--operation mode is normal

cnt_delay[0]_lut_out = A1L86 & A1L641;
cnt_delay[0] = DFFEAS(cnt_delay[0]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L222 is start_delaycnt~223
--operation mode is normal

A1L222 = !cnt_delay[1] & !cnt_delay[0];


--A1L322 is start_delaycnt~224
--operation mode is normal

A1L322 = A1L912 & A1L022 & A1L122 & A1L222;


--cnt_delay[8] is cnt_delay[8]
--operation mode is normal

cnt_delay[8]_lut_out = A1L07 & A1L641;
cnt_delay[8] = DFFEAS(cnt_delay[8]_lut_out, clk, rst, , start_delaycnt, , , , );


--cnt_delay[19] is cnt_delay[19]
--operation mode is normal

cnt_delay[19]_lut_out = A1L27 & A1L641;
cnt_delay[19] = DFFEAS(cnt_delay[19]_lut_out, clk, rst, , start_delaycnt, , , , );


--A1L641 is reduce_nor~1
--operation mode is normal

A1L641 = A1L451 # !cnt_delay[19] # !cnt_delay[8] # !A1L322;


--A1L3 is add~900
--operation mode is normal

A1L3_carry_eqn = A1L5;
A1L3 = div_reg[15] $ (A1L3_carry_eqn);


--A1L4 is add~905
--operation mode is arithmetic

A1L4_carry_eqn = A1L7;
A1L4 = div_reg[14] $ (!A1L4_carry_eqn);

--A1L5 is add~907
--operation mode is arithmetic

A1L5 = CARRY(div_reg[14] & (!A1L7));


--A1L6 is add~910
--operation mode is arithmetic

A1L6_carry_eqn = A1L9;
A1L6 = div_reg[13] $ (A1L6_carry_eqn);

--A1L7 is add~912
--operation mode is arithmetic

A1L7 = CARRY(!A1L9 # !div_reg[13]);


--A1L8 is add~915
--operation mode is arithmetic

A1L8_carry_eqn = A1L11;
A1L8 = div_reg[12] $ (!A1L8_carry_eqn);

--A1L9 is add~917
--operation mode is arithmetic

A1L9 = CARRY(div_reg[12] & (!A1L11));


--A1L01 is add~920
--operation mode is arithmetic

A1L01_carry_eqn = A1L31;
A1L01 = div_reg[11] $ (A1L01_carry_eqn);

--A1L11 is add~922
--operation mode is arithmetic

A1L11 = CARRY(!A1L31 # !div_reg[11]);


--A1L21 is add~925
--operation mode is arithmetic

A1L21_carry_eqn = A1L51;
A1L21 = div_reg[10] $ (!A1L21_carry_eqn);

--A1L31 is add~927
--operation mode is arithmetic

A1L31 = CARRY(div_reg[10] & (!A1L51));


--A1L41 is add~930
--operation mode is arithmetic

A1L41_carry_eqn = A1L71;
A1L41 = div_reg[9] $ (A1L41_carry_eqn);

--A1L51 is add~932
--operation mode is arithmetic

A1L51 = CARRY(!A1L71 # !div_reg[9]);


--A1L61 is add~935
--operation mode is arithmetic

A1L61_carry_eqn = A1L91;
A1L61 = div_reg[8] $ (!A1L61_carry_eqn);

--A1L71 is add~937