am186msr.h

ucos porting source for Am188

/******************************************************************************
 *                                                                            *
 *     AM186MSR.H                                                             *
 *                                                                            *
 *     This file contains hardware-specific declarations for                  *
 *     186EM, 186ER, and 186ES parts.                                         *
 *                                                                            *
 *                                                                            *
 ******************************************************************************
 *                                                                            *
 * Copyright 1996 Advanced Micro Devices, Inc.                                *
 *                                                                            *
 * This software is the property of Advanced Micro Devices, Inc  (AMD)  which *
 * specifically  grants the user the right to modify, use and distribute this *
 * software provided this notice is not removed or altered.  All other rights *
 * are reserved by AMD.                                                       *
 *                                                                            *
 * AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS *
 * SOFTWARE.  IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL *
 * DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR *
 * USE OF THIS SOFTWARE.                                                      *
 *                                                                            *
 * So that all may benefit from your experience, please report  any  problems *
 * or suggestions about this software back to AMD.  Please include your name, *
 * company,  telephone number,  AMD product requiring support and question or *
 * problem encountered.                                                       *
 *                                                                            *
 * Advanced Micro Devices, Inc.       Worldwide support and contact           *
 * Logic Products Division            information available at:               *
 * Systems Engineering                                                        *
 * 5204 E. Ben White Blvd.     http://www.amd.com/html/support/techsup.html   *
 * Austin, TX 78741                                                           *
 *****************************************************************************/
#ifndef _AM186ER_H_
#define _AM186ER_H_
// =====================================================================
// INTERNAL REGISTER OFFSETS

// Miscellaneous control registers
//
#define OFFS_RELC_REG      0xfe         // peripheral control block relocation
#define OFFS_RI_REG        0xfc         // refesh interval register
#define OFFS_BISTEA_REG    0xfa         // Build in self test error address
#define OFFS_BISTSC_REG    0xf8         // build in self test status/control
#define OFFS_RCFG_REG      0xf6         // reset configuration register
#define OFFS_PRL_REG       0xf4         // Processor release level register
#define OFFS_AUXC_REG      0xf2         // auxiliary cfg register (ES)
#define OFFS_PDCN_REG      0xf0         // Power-save control register
#define OFFS_WDOG_REG      0xe6         // watchdog timer register on ES
//
// Refresh control unit registers
//
#define OFFS_DRAM_ENAB     0xe4         // Enable RCU register
#define OFFS_DRAM_CLK      0xe2         // Clock prescaler register
#define OFFS_DRAM_MEM      0xe0         // Memory partition register
//
// DMA 1 registers
//
#define OFFS_DMA1_CTL      0xda         // DMA1 control register
#define OFFS_DMA1_CNT      0xd8         // DMA1 transfer count register
#define OFFS_DMA1_DSH      0xd6         // DMA1 destination addr high register
#define OFFS_DMA1_DES      0xd4         // DMA1 destination addr low register
#define OFFS_DMA1_SRH      0xd2         // DMA1 source addr high register
#define OFFS_DMA1_SRC      0xd0         // DMA1 source addr low register
//
// DMA 0 registers
//
#define OFFS_DMA0_CTL      0xca         // DMA0 control register
#define OFFS_DMA0_CNT      0xc8         // DMA0 transfer count register
#define OFFS_DMA0_DSH      0xc6         // DMA0 destination addr high register
#define OFFS_DMA0_DES      0xc4         // DMA0 destination addr low register
#define OFFS_DMA0_SRH      0xc2         // DMA0 source addr high register
#define OFFS_DMA0_SRC      0xc0         // DMA0 source addr low register
//
// Chip select registers
//
#define OFFS_CS_MPCS       0xa8         // PCS# and MCS# auxiliary register
#define OFFS_CS_MMCS       0xa6         // Midrange memory chip select reg.
#define OFFS_CS_PACS       0xa4         // Peripheral chip select register 
#define OFFS_CS_LMCS       0xa2         // lmsc register
#define OFFS_CS_UMCS       0xa0         // umcs register
#define OFFS_CS_IMCS       0xac         // Internal Memory Chip Select reg.
//
// ES Serial port 0 registers
// EM/ER Asynchronous serial port registers
//
#define OFFS_SPRT0_BDV     0x88         // serial port bauddiv reg
#define OFFS_SPRT0_RX      0x86         // serial port receive reg
#define OFFS_SPRT0_TX      0x84         // serial port transmit reg
#define OFFS_SPRT0_STAT    0x82         // serial port status reg
#define OFFS_SPRT0_CTL     0x80         // serial port control reg
#define OFFS_SPRT_BDV      0x88          // serial port bauddiv reg 
#define OFFS_SPRT_RX       0x86          // serial port receive reg
#define OFFS_SPRT_TX       0x84          // serial port transmit reg
#define OFFS_SPRT_STAT     0x82          // serial port status reg
#define OFFS_SPRT_CTL      0x80          // serial port control reg
//
// PIO registers
//
#define OFFS_PIO_DATA1     0x7a         // PIO data 1 register
#define OFFS_PIO_DIR1      0x78         // PIO direction 1 register
#define OFFS_PIO_MODE1     0x76         // PIO mode 1 register
#define OFFS_PIO_DATA0     0x74         // PIO data registers
#define OFFS_PIO_DIR0      0x72         // PIO direction register
#define OFFS_PIO_MODE0     0x70         // PIO mode 0 register
//
// Timer 2 control registers
//
#define OFFS_TMR2_CTL      0x66         // Timer 2 mode/control register
#define OFFS_TMR2_MAXA     0x62         // Timer 2 maxcount compare A register
#define OFFS_TMR2_CNT      0x60         // Timer 2 count register
//
// Timer 1 control registers
//
#define OFFS_TMR1_CTL      0x5e         // Timer 1 mode/control register
#define OFFS_TMR1_MAXB     0x5c         // Timer 1 maxcount compare B register
#define OFFS_TMR1_MAXA     0x5a         // Timer 1 maxcount compare A register
#define OFFS_TMR1_CNT      0x58         // Timer 1 count register
//
// Timer 0 control registers
//
#define OFFS_TMR0_CTL      0x56         // Timer 0 mode/control register
#define OFFS_TMR0_MAXB     0x54         // Timer 0 maxcount compare B register
#define OFFS_TMR0_MAXA     0x52         // Timer 0 maxcount compare A register
#define OFFS_TMR0_CNT      0x50         // Timer 0 count register
//
// Interrupt registers
//
#define OFFS_INT_SPRT0     0x44         // sprt 0 interrupt ctrl reg
#define OFFS_INT_SPRT1     0x42         // sprt 0 interrupt ctrl reg
#define OFFS_INT_SPRT      0x44         // serial port interrupt control reg
#define OFFS_INT_WDOG_EM   0x42         // Watchdog timer interrupt control
//
#define OFFS_INT_INT4      0x40         // INT4 control register
#define OFFS_INT_INT3      0x3e         // INT3 control register
#define OFFS_INT_INT2      0x3c         // INT2 control register
#define OFFS_INT_INT1      0x3a         // INT1 control register
#define OFFS_INT_INT0      0x38         // INT0 control register

#define OFFS_INT_DMA1      0x36         // DMA1 interrupt control register
#define OFFS_INT_DMA0      0x34         // DMA0 interrupt control register
#define OFFS_INT_INT6      OFFS_INT_DMA1 // ES only
#define OFFS_INT_INT5      OFFS_INT_DMA0 // ES only

#define OFFS_INT_TMR       0x32         // Timer interrupt control register

#define OFFS_INT_STAT      0x30         // Interrupt status register
#define OFFS_INT_IREQ      0x2e         // Interrupt request register
#define OFFS_INT_INSV      0x2c         // In-service register
#define OFFS_INT_PMSK      0x2a         // Priority mask register
#define OFFS_INT_MASK      0x28         // Interrupt mask register
#define OFFS_INT_PSTT      0x26         // Poll status register
#define OFFS_INT_POLL      0x24         // Poll register
#define OFFS_INT_EOI       0x22         // End-of-interrupt register
#define OFFS_INT_VEC       0x20         // Interrupt vector register
//
// ES Serial port 1 register
// EM/ER Synchronous serial port register
//
#define OFFS_SPRT1_BDV     0x18         // serial port bauddiv reg
#define OFFS_SPRT1_RX      0x16         // serial port receive reg
#define OFFS_SPRT1_TX      0x14         // serial port transmit reg
#define OFFS_SPRT1_STAT    0x12         // serial port status reg
#define OFFS_SPRT1_CTL     0x10         // serial port control reg

#define OFFS_SS_RX         0x18         // Synchronous serial receive register
#define OFFS_SS_TX0        0x16         // Synchronous serial transmit 0 reg.
#define OFFS_SS_TX1        0x14         // Synchronous serial transmit 1 reg.
#define OFFS_SS_CTL        0x12         // Synchronous serial control register
#define OFFS_SS_STAT       0x10         // Synchronous serial status register


//
// ======================================================================
// STANDARD EXTERNAL-MEMORY SEGMENT AND OFFSET MAP

#define CTL_OFF            0xff00        // Ctl reg offset for peripherals
#define DEF_RLC_OFF        0x00ff        // (ES) 0ffh is default A20-A28


// Miscellaneous control registers
//
#define RELC_REG           (CTL_OFF+OFFS_RELC_REG)
#define RI_REG             (CTL_OFF+OFFS_RI_REG)
#define BISTEA_REG         (CTL_OFF+OFFS_BISTEA_REG)
#define BISTSC_REG         (CTL_OFF+OFFS_BISTSC_REG)
#define RCFG_REG           (CTL_OFF+OFFS_RCFG_REG)
#define PRL_REG            (CTL_OFF+OFFS_PRL_REG)
#define AUXC_REG           (CTL_OFF+OFFS_AUXC_REG)  // ES only
#define PDCN_REG           (CTL_OFF+OFFS_PDCN_REG)
#define WDOG_REG           (CTL_OFF+OFFS_WDOG_REG)  // ES only
//
// Refresh control unit registers
//
#define DRAM_ENAB          (CTL_OFF+OFFS_DRAM_ENAB)
#define DRAM_CLK           (CTL_OFF+OFFS_DRAM_CLK)
#define DRAM_MEM           (CTL_OFF+OFFS_DRAM_MEM)
//
// DMA 1 registers
//
#define DMA1_CTL           (CTL_OFF+OFFS_DMA1_CTL)
#define DMA1_CNT           (CTL_OFF+OFFS_DMA1_CNT)
#define DMA1_DSH           (CTL_OFF+OFFS_DMA1_DSH)
#define DMA1_DES           (CTL_OFF+OFFS_DMA1_DES)
#define DMA1_SRH           (CTL_OFF+OFFS_DMA1_SRH)
#define DMA1_SRC           (CTL_OFF+OFFS_DMA1_SRC)
//
// DMA 0 registers
//
#define DMA0_CTL           (CTL_OFF+OFFS_DMA0_CTL)
#define DMA0_CNT           (CTL_OFF+OFFS_DMA0_CNT)
#define DMA0_DSH           (CTL_OFF+OFFS_DMA0_DSH)
#define DMA0_DES           (CTL_OFF+OFFS_DMA0_DES)
#define DMA0_SRH           (CTL_OFF+OFFS_DMA0_SRH)
#define DMA0_SRC           (CTL_OFF+OFFS_DMA0_SRC)
//
// Chip select registers
//
#define CS_MPCS            (CTL_OFF+OFFS_CS_MPCS)
#define CS_MMCS            (CTL_OFF+OFFS_CS_MMCS)
#define CS_PACS            (CTL_OFF+OFFS_CS_PACS)
#define CS_LMCS            (CTL_OFF+OFFS_CS_LMCS)
#define CS_UMCS            (CTL_OFF+OFFS_CS_UMCS)
#define CS_IMCS            (CTL_OFF+OFFS_CS_IMCS)
//
// ES Serial port 0 registers
// EM/ER Asynchronous serial port  registers
//
#define SPRT0_BDV          (CTL_OFF+OFFS_SPRT0_BDV)
#define SPRT0_RX           (CTL_OFF+OFFS_SPRT0_RX)
#define SPRT0_TX           (CTL_OFF+OFFS_SPRT0_TX)
#define SPRT0_STAT         (CTL_OFF+OFFS_SPRT0_STAT)
#define SPRT0_CTL          (CTL_OFF+OFFS_SPRT0_CTL)
#define SPRT_BDV           (CTL_OFF+OFFS_SPRT_BDV)
#define SPRT_RX            (CTL_OFF+OFFS_SPRT_RX)
#define SPRT_TX            (CTL_OFF+OFFS_SPRT_TX)
#define SPRT_STAT          (CTL_OFF+OFFS_SPRT_STAT)
#define SPRT_CTL           (CTL_OFF+OFFS_SPRT_CTL)
//
// PIO registers
//
#define PIO_DATA1          (CTL_OFF+OFFS_PIO_DATA1)
#define PIO_DIR1           (CTL_OFF+OFFS_PIO_DIR1)
#define PIO_MODE1          (CTL_OFF+OFFS_PIO_MODE1)
#define PIO_DATA0          (CTL_OFF+OFFS_PIO_DATA0)
#define PIO_DIR0           (CTL_OFF+OFFS_PIO_DIR0)
#define PIO_MODE0          (CTL_OFF+OFFS_PIO_MODE0)
//
// Timer 2 control registers
//
#define TMR2_CTL           (CTL_OFF+OFFS_TMR2_CTL)
#define TMR2_MAXA          (CTL_OFF+OFFS_TMR2_MAXA)
#define TMR2_CNT           (CTL_OFF+OFFS_TMR2_CNT)
//
// Timer 1 control registers
//
#define TMR1_CTL           (CTL_OFF+OFFS_TMR1_CTL)
#define TMR1_MAXB          (CTL_OFF+OFFS_TMR1_MAXB)
#define TMR1_MAXA          (CTL_OFF+OFFS_TMR1_MAXA)
#define TMR1_CNT           (CTL_OFF+OFFS_TMR1_CNT)
//
// Timer 0 control registers
//
#define TMR0_CTL           (CTL_OFF+OFFS_TMR0_CTL)
#define TMR0_MAXB          (CTL_OFF+OFFS_TMR0_MAXB)
#define TMR0_MAXA          (CTL_OFF+OFFS_TMR0_MAXA)
#define TMR0_CNT           (CTL_OFF+OFFS_TMR0_CNT)
//