irq.h

ucos porting source for Am188

/**************************************************************************
		These are the port addresses of the 8259 Programmable Interrupt
		Controller (PIC).
***************************************************************************/

#define F_IMR         0x21     /* First Interrupt Mask Register port */
#define F_ICR         0x20     /* First Interrupt Control Port       */

#define S_IMR         0xA1     /* Secondary Interrupt Mask Register port */
#define S_ICR         0xA0     /* Secondary Interrupt Control Port       */

/**************************************************************************
		An end of interrupt needs to be sent to the Control Port of
		the 8259 when a hardware interrupt ends.
***************************************************************************/

#define EOI         0x20      /* End Of Interrupt */

/*************************************************************************
		The (IMR) tells the (PIC) to service an interrupt only if it
		is not masked (FALSE).
*************************************************************************/

#define IRQ0        0xFE
#define IRQ1        0xFD
#define IRQ2        0xFB
#define IRQ3        0xF7        /* COM2 */
#define IRQ4        0xEF        /* COM1 */
#define IRQ5        0xDF
#define IRQ6        0xBF
#define IRQ7        0x7F
#define IRQ8        0xFE
#define IRQ9        0xFD
#define IRQ10       0xFB
#define IRQ11       0xF7
#define IRQ12       0xEF
#define IRQ13       0xDF
#define IRQ14       0xBF
#define IRQ15       0x7F

#define IRQ0VECT    0x08        /* TIMER */
#define IRQ1VECT    0x09        /* KEYBOARD */
#define IRQ2VECT    0x0A        /* SECONDARY PIC */
#define IRQ3VECT    0x0B        /* COM2, 4 */
#define IRQ4VECT    0x0C        /* COM1, 3 */
#define IRQ5VECT    0x0D        /* PRIMARY HARD DISK */
#define IRQ6VECT    0x0E        /* FLOPY DISK */
#define IRQ7VECT    0x0F        /* PRINTER */
#define IRQ8VECT    0x70        /* RTC */
#define IRQ9VECT    0x71
#define IRQ10VECT   0x72
#define IRQ11VECT   0x73
#define IRQ12VECT   0x74
#define IRQ13VECT   0x75        /* 80237 NMI */
#define IRQ14VECT   0x76        /* SECONDARY HARD DISK */
#define IRQ15VECT   0x77

#define     IntMask0     0x01        /* INTERRUPT MASK0 */
#define     IntMask1     0x02        /* INTERRUPT MASK1 */
#define     IntMask2     0x04        /* INTERRUPT MASK2 */
#define     IntMask3     0x08        /* INTERRUPT MASK3 */
#define     IntMask4     0x10        /* INTERRUPT MASK4 */
#define     IntMask5     0x20        /* INTERRUPT MASK5 */
#define     IntMask6     0x40        /* INTERRUPT MASK6 */
#define     IntMask7     0x80        /* INTERRUPT MASK7 */
#define     IntMask8     0x01        /* INTERRUPT MASK8 */
#define     IntMask9     0x02        /* INTERRUPT MASK9 */
#define     IntMask10    0x04        /* INTERRUPT MASK10 */
#define     IntMask11    0x08        /* INTERRUPT MASK11 */
#define     IntMask12    0x10        /* INTERRUPT MASK12 */
#define     IntMask13    0x20        /* INTERRUPT MASK13 */
#define     IntMask14    0x40        /* INTERRUPT MASK14 */
#define     IntMask15    0x80        /* INTERRUPT MASK15 */