scc8530.h

ucos porting source for Am188

/************************************************************************/
/* PROGRAMER: CHAE,BYOUNG-CHEOL                                         */
/* PROGRAM  : SCC8530.H                                                 */
/* COMPILER : BORLAND C/C++ 3.1 FOR DOS 								*/
/************************************************************************/

#define     SCCBASE_BC   0x1000
#define     SCCBASE_BD   0x1001

#define     SCCBASE_AC   0x1002
#define     SCCBASE_AD   0x1003

#define     RR0         0x00
#define     RR1         0x01
#define     RR2         0x02
#define     RR3         0x03
#define     RR6         0x06
#define     RR7         0x07
#define     RR8         0x08
#define     RR10        0x0A
#define     RR12        0x0C
#define     RR13        0x0E
#define     RR15        0x0F

#define     WR0         0x00
#define     WR1         0x01
#define     WR2         0x02
#define     WR3         0x03
#define     WR4         0x04
#define     WR5         0x05
#define     WR6         0x06
#define     WR7         0x07
#define     WR8         0x08
#define     WR9         0x09
#define     WR10        0x0A
#define     WR11        0x0B
#define     WR12        0x0C
#define     WR13        0x0D
#define     WR14        0x0E
#define     WR15        0x0F


/* define   WR0 : COMMAND REGISTER */
#define     NULL_CODE           0x00
#define     RESET_INT           0x10
#define     SEND_ABORT          0x18
#define     ENABLE_INT_NEXT_RX  0x20
#define     RESET_TXINT_PENDING 0x28
#define     RESET_ERROR         0x30
#define     RESET_IUS           0x38

#define     RESET_RX_CRC_CHECKER    0x40
#define     RESET_TX_CRC_GENERATOR  0x80
#define     RESET_TX_UNDERRUN       0xC0
#define     RESET_EOM_LATCH         0xC0

/* define   WR1 : Tx & Rx Interrupt mode and Transfer Mode */
#define     EXT_INT             0x01
#define     SCC_TX_INT          0x02
#define     PARITY_SPECIAL      0x04
#define     RX_INT_FIRST        0x80
#define     SCC_RX_INT          0x10
#define     RX_INT_SPECIAL      0x18
#define     WAIT_DMA_REQ        0x20
#define     WAIT_DMA_REQ_FUNC   0x40
#define     WAIT_DMA_REQ_EN     0x80

/* define   WR3 : Receive Parameters and Control */
#define     RX_ENABLE           0x01
#define     SYNC_CHAR_LOAD_INH  0x02
#define     ADDR_SEARCH_MODE    0x04    // SDLC MODE
#define     RX_CRC_ENABLE       0x08

#define     HUNT_MODE           0x10
#define     AUTO_ENABLES        0x20

#define     RX5                 0x00
#define     RX7                 0x40
#define     RX6                 0x80
#define     RX8                 0xC0

/* define   WR4 : Tx & Rx Miscellaneous Parameters and Modes */
#define     PARITY_ENABLE       0x01
#define     PARITY_EVEN         0x02
#define     PARITY_ODD          0x00

#define     SYNC_MODE           0x00
#define     _1STOP              0x04
#define     _15STOP             0x08
#define     _2STOP              0x0C

#define     _8BIT_SYNC          0x00
#define     _16BIT_SYNC         0x10
#define     SDLC_MODE           0x20
#define     EXTERNAL_SYNC_MODE  0x30

#define     X1_CLOCK            0x00
#define     X16_CLOCK           0x40
#define     X32_CLOCK           0x80
#define     X64_CLOCK           0xC0

/* define   WR5 : Tx Parameters and Controls */
#define     TX_CRC_ENABLE       0x01
#define     SCC_RTS             0x02
#define     CRC_16              0x04
#define     TX_ENABLE           0x08
#define     SEND_BREAK          0x10

#define     TX5                 0x00
#define     TX7                 0x20
#define     TX6                 0x40
#define     TX8                 0x60

#define     SCC_DTR             0x80

/* define   WR9 : Master Interrupt Control */
#define     VIS                 0x01
#define     NV                  0x02
#define     DLC                 0x04
#define     MIE                 0x08
#define     STATUS_HL           0x10
#define     INTACK_ENABLE       0x20

#define     NO_RESET            0x00
#define     CHANNEL_RESET_B     0x40
#define     CHANNEL_RESET_A     0x80
#define     FORCE_RESET         0xC0

/* define   WR10 : Miscellaneous Tx & Rx Controls */
#define     _6_8BIT_SYNC            0x01
#define     LOOP_MODE               0x02
#define     ABORT_FLAG_ON_UNDERRUN  0x04
#define     MARK_FLAG_IDLE          0x08
#define     GO_ACTIVE_ON_POLL       0x10

#define     NRZ                     0x00
#define     NRZI                    0x20
#define     FM1                     0x40
#define     FM0                     0x60

#define     CRC_PRESET              0x80

/* define   WR11 : Clock Mode Control */
// TRxC output
#define     XTAL                0x00
#define     TRANSMIT_CLOCK      0x01
#define     BR_GENERATOR        0x02
#define     DPLL                0x03

#define     TRxC_OUTPUT         0x04

// Transmit Clock
#define     T_RTxC              0x00
#define     T_TRxC              0x08
#define     T_BR_GEN            0x10
#define     T_DPLL              0x18

// Receive Clock
#define     R_RTxC              0x00
#define     R_TRxC              0x20
#define     R_BR_GEN            0x40
#define     R_DPLL              0x60

#define     RTxC_XTAL           0x80

/* define   WR14 : Miscellaneous Control Bits */
#define     BR_GEN_ENABLE       0x01
#define     BR_GEN_SOURCE       0x02
#define     DTR_REQ             0x04
#define     AUTO_ECHO           0x08
#define     LOCAL_LOOPBACK      0x10

#define     NULL_COMMAND        0x00
#define     ENTER_SEARCH_MODE   0x20
#define     RESET_MISSING_CLOCK 0x40
#define     DISABLE_DPLL        0x60
#define     SRC_BR              0x80
#define     SRC_RTxC            0xA0
#define     FM_MODE             0xC0
#define     NRZI_MODE           0xE0

/* define   WR15 : External / Status Interrupt Control */
#define     WR7_PRIME           0x01
#define     ZERO_COUNT_IE       0x02
#define     SDLC_FIFO_ENABLE    0x04
#define     DCD_IE              0x08
#define     SYNC_HUNT_IE        0x10
#define     CTS_IE              0x20
#define     TX_UNDERRUN_IE      0x40
#define     EOM_IE              0x40
#define     BREAK_IE            0x80
#define     ABORT_IE            0x80

/* define   RR0 : Transmit/Receive Buffer Status and External Status */
#define     RX_CHAR_AVAILABLE   0x01
#define     ZERO_COUNT          0x02
#define     TXB_EMPTY           0x04
#define     SCC_DCD             0x08
#define     SYNC_HUNT           0x10
#define     SCC_CTS             0x20

#define     Tx_UNDERRUN         0x40
#define     EOM                 0x40

#define     BREAK               0x80
#define     ABORT               0x80

/* define   RR1 : Special Condition ststus and SDLC(End of Frame) */
#define     ALL_SENT            0x01
#define     RESIDUE_CODE2       0x02
#define     RESIDUE_CODE1       0x04
#define     RESIDUE_CODE0       0x08

#define     PARITY_ERROR        0x10
#define     RxOVERRUN_ERROR     0x20
#define     CRC_FRMAING_ERROR   0x40
#define     END_OF_FRAMMIG      0x80

/* define   RR3 : Interrupt Pending register */
#define     CHANNEL_B_EXT_IP    0x01
#define     CHANNEL_B_TX_IP     0x02
#define     CHANNEL_B_RX_IP     0x04

#define     CHANNEL_A_EXT_IP    0x08
#define     CHANNEL_A_TX_IP     0x10
#define     CHANNEL_A_RX_IP     0x20

/* define   RR10 : Some Miscellaneous ststus bits */
#define     ON_LOOP             0x02
#define     LOOP_SENDING        0x10
#define     _2CLOCK_MISSING     0x40
#define     _1CLOCK_MISSING     0x80

#define     SCC_BUF_SIZE        1024

typedef struct
{
    word head;
    word tail;
    unsigned char RxBuffer[SCC_BUF_SIZE];
} _SCC;

extern _SCC SCC[4];
extern byte WR[16], RR[16];

extern void SCC_write_command(int channel, byte waddr, byte wd);
extern byte SCC_read_status(int channel, byte raddr);
extern void SCC_write_data(int channel, byte wd);
extern byte SCC_read_data(int channel);

extern void SCC_Initialize(int, word, int, char, int);
extern void SCC_Putchar(int port, byte tc);
extern int  SCC_Getchar(int port, byte *rc);
extern void SCC_ClearBuffer(int port);
extern int  SCC_DtrControl(int port, int on_off);