📄 am186msr.inc
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INT_REQ_INT1 equ INT_INSV_INT1
INT_REQ_INT0 equ INT_INSV_INT0
INT_REQ_DMA1 equ INT_INSV_DMA1
INT_REQ_DMA0 equ INT_INSV_DMA0
INT_REQ_TMR equ INT_INSV_TMR
;
; -------------------------------------------------------------
; PIO PINS
PIO0_TMRI1 equ 00001h ; PIO 0
PIO0_TMRO1 equ 00002h ; PIO 1
PIO0_PCS6 equ 00004h ; PIO 2
PIO0_PCS5 equ 00008h ; PIO 3
PIO0_DTR equ 00010h ; PIO 4
PIO0_DEN equ 00020h ; PIO 5
PIO0_SRDY equ 00040h ; PIO 6
PIO0_A17 equ 00080h ; PIO 7
PIO0_A18 equ 00100h ; PIO 8
PIO0_A19 equ 00200h ; PIO 9
PIO0_TMRO0 equ 00400h ; PIO 10
PIO0_TMRI0 equ 00800h ; PIO 11
PIO0_DRQ0 equ 01000h ; PIO 12
PIO0_DRQ1 equ 02000h ; PIO 13
PIO0_MCS0 equ 04000h ; PIO 14
PIO0_MCS1 equ 08000h ; PIO 15
PIO1_PCS0 equ 00001h ; PIO 16
PIO1_PCS1 equ 00002h ; PIO 17
PIO1_PCS2 equ 00004h ; PIO 18
PIO1_PCS3 equ 00008h ; PIO 19
PIO1_SCLK equ 00010h ; PIO 20
PIO1_SDATA equ 00020h ; PIO 21
PIO1_SDEN0 equ 00040h ; PIO 22
PIO1_SDEN1 equ 00080h ; PIO 23
PIO1_MCS2 equ 00100h ; PIO 24
PIO1_MCS3 equ 00200h ; PIO 25
PIO1_UZI equ 00400h ; PIO 26
PIO1_TX equ 00800h ; PIO 27
PIO1_RX equ 01000h ; PIO 28
PIO1_S6 equ 02000h ; PIO 29
PIO1_INT4 equ 04000h ; PIO 30
PIO1_INT2 equ 08000h ; PIO 31
;
;
; Asynchronous serial port control register (SPRT_CTL)
;
SPRT_CTL_TXIE equ 00800h ; enable transmit intrpt
SPRT_CTL_RXIE equ 00400h ; enable receive intrpt
SPRT_CTL_LOOP equ 00200h ; enable loop-back mode
SPRT_CTL_BRK equ 00100h ; send break or *break
SPRT_CTL_BRKHIGH equ 00080h ; break value is high
SPRT_CTL_BRKLOW equ 00000h ; break value is low
SPRT_CTL_NOPARITY equ 00000h ; no parity bit
SPRT_CTL_EVEN equ 00060h ; even parity
SPRT_CTL_ODD equ 00040h ; odd parity
SPRT_CTL_8BITS equ 00010h ; char lengt is 8 bits
SPRT_CTL_7BITS equ 00000h ; char lengt is 7 bits
SPRT_CTL_2STOP equ 00008h ; two stop bits
SPRT_CTL_1STOP equ 00000h ; one stop bit
SPRT_CTL_TX equ 00004h ; enable transmitter
SPRT_CTL_RSIE equ 00002h ; enable Rx error intrpts
SPRT_CTL_RX equ 00001h ; enable receiver
;
; Asynchronous serial port status register (SPRT_STAT)
;
SPRT_STAT_TEMT equ 00040h ; transmitter is empty
SPRT_STAT_THRE equ 00020h ; Tx holding reg. empty
SPRT_STAT_RDR equ 00010h ; receive char ready
SPRT_STAT_BRK equ 00008h ; break received
SPRT_STAT_FRAME equ 00004h ; framing error detected
SPRT_STAT_PARITY equ 00002h ; parity error detected
SPRT_STAT_OVERFLOW equ 00001h ; receive overflow
SPRT_STAT_ERROR equ SPRT_STAT_BRK+SPRT_STAT_FRAME+SPRT_STAT_PARITY+SPRT_STAT_OVERFLOW
; -----------------------------------------------------------------------
; DMA Control Registers (1&2 - 0xda, 0xca)
DMA_DEST_MEM equ 08000h ; DMA dest. 1=memory, 0=I/O space
DMA_DEST_DEC equ 04000h ; decrement DMA dest addr
DMA_DEST_INC equ 02000h ; increment DMA dest addr
DMA_SRC_MEM equ 01000h ; DMA source 1=memory, 0=I/O space
DMA_SRC_DEC equ 00800h ; decrement DMA src addr
DMA_SRC_INC equ 00400h ; increment DMA src addr
DMA_TC equ 00200h ; DMA uses terminal count
DMA_INT equ 00100h ; intrpt on terminal count
DMA_SYN1 equ 00080h ; 1=Src. Sync.2=Dest. Sync.3=Undef.
DMA_SYN0 equ 00040h ; SYN1:0 0x = Unsynchronized
DMA_P equ 00020h ; if set, channel=hi prio.,else low
DMA_IDRQ equ 00010h ; if set, use timer 2
DMA_CHG equ 00004h ; set before DMA_STRT can be set
DMA_STRT equ 00002h ; if set, DMA channel is "armed"
DMA_WORD equ 00001h ; if set, word transfers, else byte
DMA_BYTE equ 00000h ; Byte transfers
; some common combinations
DMA_S_MEM_INC equ DMA_SRC_MEM+DMA_SRC_INC
DMA_D_MEM_INC equ DMA_DEST_MEM+DMA_DEST_INC
DMA_S_D_MEM_INC equ DMA_S_MEM_INC+DMA_D_MEM_INC
DMA_ARM equ DMA_CHG+DMA_STRT
DMA_DEST_CONST equ 00000h ; DMA destination addr is constant
DMA_SRC_IO equ 00000h ; DMA source is in I/O space
DMA_SRC_CONST equ 00000h ; DMA source addr is constant
DMA_DEST_IO equ 00000h ; DMA destination is in I/O space
DMA_UNSYNC equ 00000h ; unsynchronized transfers
DMA_SRCSYNC equ 000c0h ; source synchronized transfers
DMA_DESTSYNC equ 00080h ; destination synchronized transfers
DMA_HIGHPRI equ 00040h ; channel is high priority
DMA_LOWPRI equ 00000h ; channel is low priority
;
; -------------------------------------------------------------
; CHIP-SELECT REGISTERS
; Fields used by more than one of the chip select registers
CS_WAIT0 equ 00000h ; zero wait states
CS_WAIT1 equ 00001h ; one wait state
CS_WAIT2 equ 00002h ; two wait states
CS_WAIT3 equ 00003h ; three wait states
CS_IGXRDY equ 00004h ; ignore external ready
; The following wait states can only be used for PCS3-0 - set in
; the PACS register (CS_PACS).
;
CS_MPCS_WAIT5 equ 00008h ; five wait states
CS_MPCS_WAIT7 equ 00009h ; seven wait states
CS_MPCS_WAIT9 equ 0000ah ; nine wait states
CS_MPCS_WAIT15 equ 0000bh ; fifteen wait states
; The following bits are only on LCS (CS_LMCS) and UCS (CS_UMCS)
CS_DISADDR equ 00080h ; disable AD addr output
CS_DRAM_ENABLE equ 00040h ; enable DRAM on 186ED
;
; UMCS (upper memory) register
CS_UMCS_64K equ 07000h ; UCS is 64K
CS_UMCS_128K equ 06000h ; UCS is 128K
CS_UMCS_256K equ 04000h ; UCS is 256K
CS_UMCS_512K equ 00000h ; UCS is 512K
;
; LMCS (lower memory) register
CS_LMCS_PSRAM equ 00040h ; turn off PSRAM when subtracted out
CS_LMCS_64K equ 00000h ; LCS is 64K (0 - 0ffffh)
CS_LMCS_128K equ 01000h ; LCS is 128K (0 - 1ffffh)
CS_LMCS_256K equ 03000h ; LCS is 256K (0 - 3ffffh)
CS_LMCS_512K equ 07000h ; LCS is 512K (0 - 7ffffh)
CS_LMCS_PSEN equ 00040h ; enable PSRAM support
;
; IMCS (internal memory) register
CS_IMCS_SHOW_READ equ 00400h ; show read enable
CS_IMCS_RAM_ENABLE equ 00200h ; ram enable
CS_IMCS_RESERVED equ 000ffh ; reserved set to 1
;
; MPCS register bits
;
CS_MPCS_EX equ 00080h
CS_MPCS_MS equ 00040h
CS_MPCS_EXWT equ 00008h ; EXTENDED PCS WAIT STATES
CS_MPCS_8K equ 00100h
CS_MPCS_16K equ 00200h
CS_MPCS_32K equ 00400h
CS_MPCS_64K equ 00800h
CS_MPCS_128K equ 01000h
CS_MPCS_256K equ 02000h
CS_MPCS_512K equ 04000h
CS_MPCS_PCS_ADDR equ 00000h ; PCS6-5 are addr lines
;
; MMCS register bits
;
CS_MMCS_8K equ 00200h
CS_MMCS_16K equ 00400h
CS_MMCS_32K equ 00800h
CS_MMCS_64K equ 01000h
CS_MMCS_96K equ 01800h
CS_MMCS_128K equ 02000h
CS_MMCS_256K equ 04000h
CS_MMCS_512K equ 08000h
CS_MMCS_704K equ 0b000h
CS_MMCS_896K equ 0e000h
;
; -------------------------------------------------------------
; Timer register (1&2 - 0x56, 0x5e)
TMR_ENABLE equ 08000h
TMR_INH equ 04000h
TMR_INT equ 02000h ; generate intrpt rest
TMR_RIU equ 01000h ; ax count reached flag
TMR_MC equ 00020h ; max count reached flag
TMR_RTG equ 00010h ; retrigger bit
TMR_2PRES equ 00008h ; timer 2 is a prescaler
TMR_EXT equ 00004h ; use external timer
TMR_ALT equ 00002h
TMR_CONT equ 00001h ; continuous mode
TMR_START equ TMR_ENABLE+TMR_INH ; start timer
; These fields apply to master mode interrupt control registers
; Priorities also apply to interrupt priority register (INT_PMSK)
INT_PRI0 equ 00000h ; highest priority
INT_PRI1 equ 00001h ; priority = 1
INT_PRI2 equ 00002h ; priority = 2
INT_PRI3 equ 00003h ; priority = 3
INT_PRI4 equ 00004h ; priority = 4
INT_PRI5 equ 00005h ; priority = 5
INT_PRI6 equ 00006h ; priority = 6
INT_PRI7 equ 00007h ; lowest priority
INT_DISABLE equ 00008h ; disable interrupt
INT_ENABLE equ 00000h ; enable interrupt
INT_LEVEL equ 00010h ; level triggered mode
INT_EDGE equ 00000h ; edge triggered mode
; These two fields apply only to INT_INT0 and INT_INT1
INT_CASCADE equ 00020h ; cascade mode enable
INT_SFNM equ 00040h ; specl fully nested mode
; Interrupt Status Register fields (INT_STAT)
INT_DHLT equ 08000h ; halt DMA activity
INT_STAT_TMR2 equ 00004h ; TMR2 has intrpt pending
INT_STAT_TMR1 equ 00002h ; TMR1 has intrpt pending
INT_STAT_TMR0 equ 00001h ; TMR0 has intrpt pending
;
; These fields apply to the interrupt request register (INT_IREQ),
; the interrupt in-service register (INT_INSV), and the interrupt
; mask register (INT_MASK)
INT_SPT0 equ 00400h ; serial port
INT_WATCHDOG equ 00200h ; watchdog timer
INT_I4 equ 00100h ; INT4
INT_I3 equ 00080h ; INT3
INT_I2 equ 00040h ; INT2
INT_I1 equ 00020h ; INT1
INT_I0 equ 00010h ; INT0
INT_D1 equ 00008h ; DMA1
INT_D0 equ 00004h ; DMA0
INT_TIMER equ 00001h ; any timer (see INT_STAT)
; EOI register fields
EOI_NONSPEC equ 08000h ; non-specific EOI
; Interrupt poll and poll status register fields
INT_POLL_IREQ equ 08000h ; interrupt pending flag
; Synchronous serial port status register fields (SS_STAT)
SS_STAT_ERR equ 00004h ; error flag
SS_STAT_COMPLETE equ 00002h ; transaction complete
SS_STAT_BUSY equ 00001h ; SS port busy flag
; Synchronous serial port control register fields (SS_CTL)
SS_CTL_CLK2 equ 00000h ; SS clck = 1/2 proc clck
SS_CTL_CLK4 equ 00010h ; SS clck = 1/4 proc clck
SS_CTL_CLK8 equ 00020h ; SS clck = 1/8 proc clck
SS_CTL_CLK16 equ 00030h ; SS clck = 1/16proc clck
SS_CTL_DEN0 equ 00001h ; SDEN0 Enable
SS_CTL_DEN1 equ 00002h ; SDEN0 Enable
;
; ======================================================================
; Interrupt types
; These are the values to write to the EOI register
EOITYPE_TMR0 equ 008h
EOITYPE_TMR1 equ EOITYPE_TMR0
EOITYPE_TMR2 equ EOITYPE_TMR0
EOITYPE_DMA0 equ 00ah
EOITYPE_DMA1 equ 00bh
EOITYPE_INT0 equ 00ch
EOITYPE_INT1 equ 00dh
EOITYPE_INT2 equ 00eh
EOITYPE_INT3 equ 00fh
EOITYPE_INT4 equ 010h
EOITYPE_INT5 equ EOITYPE_DMA0
EOITYPE_INT6 equ EOITYPE_DMA1
EOITYPE_SPRT equ 014h
EOITYPE_SPRT0 equ 014h
EOITYPE_WDOG equ 011h
EOITYPE_INT11 equ 011h
EOITYPE_NONSPEC equ 08000h
ITYPE_DIV equ 00h ; Divide error
ITYPE_TRACE equ 01h ; trace trap
ITYPE_NMI equ 02h ; non-maskable interrupt
ITYPE_BREAK equ 03h ; breakpoint
ITYPE_OVERFLOW equ 04h ; overflow
ITYPE_BOUNDS equ 05h ; bound
ITYPE_ILLOP equ 06h ; illegal opcode
ITYPE_ESC equ 07h ; ESC
ITYPE_TMR0 equ EOITYPE_TMR0 ; Timer 0
ITYPE_TMR1 equ 012h ; Timer 1
ITYPE_TMR2 equ 013h ; Timer 2
ITYPE_DMA0 equ EOITYPE_DMA0 ; DMA 0
ITYPE_DMA1 equ EOITYPE_DMA1 ; DMA 1
ITYPE_INT0 equ EOITYPE_INT0 ; INT0
ITYPE_INT1 equ EOITYPE_INT1 ; INT1
ITYPE_INT2 equ EOITYPE_INT2 ; INT2
ITYPE_INT3 equ EOITYPE_INT3 ; INT3
ITYPE_INT4 equ EOITYPE_INT4 ; INT4
ITYPE_SPRT equ EOITYPE_SPRT ; Serial Port 0
ITYPE_SPRT0 equ EOITYPE_SPRT0 ; Serial Port 0
ITYPE_WDOG equ EOITYPE_WDOG ; Watchdog timer
ITYPE_SPRT equ EOITYPE_SPRT ; Asynchronous serial port
;
; -----------------------------------------------------------------------
; Baud rate constants
BAUD300at20 equ 2082
BAUD300at25 equ 2603
BAUD300at33 equ 3471
BAUD300at40 equ 4165
BAUD600at20 equ 1040
BAUD600at25 equ 1301
BAUD600at33 equ 1735
BAUD600at40 equ 2082
BAUD1200at20 equ 519
BAUD1200at25 equ 650
BAUD1200at33 equ 867
BAUD1200at40 equ 1040
BAUD2400at20 equ 259
BAUD2400at25 equ 324
BAUD2400at33 equ 433
BAUD2400at40 equ 519
BAUD4800at20 equ 129
BAUD4800at25 equ 161
BAUD4800at33 equ 216
BAUD4800at40 equ 259
BAUD9600at20 equ 64
BAUD9600at25 equ 80
BAUD9600at33 equ 107
BAUD9600at40 equ 129
BAUD14400at20 equ 42
BAUD14400at25 equ 53
BAUD14400at33 equ 71
BAUD14400at40 equ 85
BAUD19200at20 equ 31
BAUD19200at25 equ 39
BAUD19200at33 equ 53
BAUD19200at40 equ 64
;
; -----------------------------------------------------------------------
; ES-specific watch dog register values
WDOG_REG_ES EQU 0FFE6h
WDOG_WR1_ES EQU 03333h
WDOG_WR2_ES EQU 0cccch
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