📄 am186msr.inc
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;*****************************************************************************
; Copyright 1995 Advanced Micro Devices, Inc.
;
; This software is the property of Advanced Micro Devices, Inc (AMD) which
; specifically grants the user the right to modify, use and distribute this
; software provided this notice is not removed or altered. All other rights
; are reserved by AMD.
;
; AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
; SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL
; DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR
; USE OF THIS SOFTWARE.
;
; So that all may benefit from your experience, please report any problems
; or suggestions about this software to:
;
; Advanced Micro Devices, Inc.
; Embedded Processor Division
; Mail Stop 590
; 5900 E. Ben White Blvd.
; Austin, TX 78741
; (800) 222-9323
;****************************************************************************/
;*****************************************************************************
;
; am186er.ah
;
; Header file for defines specific to processor and board.
;
; Created: 12/95 MT
;
; Modified:
; Date Initials Comment
;
;
;****************************************************************************/
; =====================================================================
; INTERNAL REGISTER OFFSETS
; Miscellaneous control registers
;
OFFS_RELC_REG equ 0feh ; peripheral control block relocation
OFFS_RI_REG equ 0fch ; refesh interval register
OFFS_BISTEA_REG equ 0fah ; Build in self test error address
OFFS_BISTSC_REG equ 0f8h ; build in self test status/control
OFFS_RCFG_REG equ 0f6h ; reset configuration register
OFFS_PRL_REG equ 0f4h ; Processor release level register
OFFS_PDCN_REG equ 0f0h ; Power-save control register
;
; Refresh control unit registers
;
OFFS_DRAM_ENAB equ 0e4h ; Enable RCU register
OFFS_DRAM_CLK equ 0e2h ; Clock prescaler register
OFFS_DRAM_MEM equ 0e0h ; Memory partition register
;
; DMA 1 registers
;
OFFS_DMA1_CTL equ 0dah ; DMA1 control register
OFFS_DMA1_CNT equ 0d8h ; DMA1 transfer count register
OFFS_DMA1_DSH equ 0d6h ; DMA1 destination addr high register
OFFS_DMA1_DES equ 0d4h ; DMA1 destination addr low register
OFFS_DMA1_SRH equ 0d2h ; DMA1 source addr high register
OFFS_DMA1_SRC equ 0d0h ; DMA1 source addr low register
;
; DMA 0 registers
;
OFFS_DMA0_CTL equ 0cah ; DMA0 control register
OFFS_DMA0_CNT equ 0c8h ; DMA0 transfer count register
OFFS_DMA0_DSH equ 0c6h ; DMA0 destination addr high register
OFFS_DMA0_DES equ 0c4h ; DMA0 destination addr low register
OFFS_DMA0_SRH equ 0c2h ; DMA0 source addr high register
OFFS_DMA0_SRC equ 0c0h ; DMA0 source addr low register
;
; Chip select registers
;
OFFS_CS_MPCS equ 0a8h ; PCS# and MCS# auxiliary register
OFFS_CS_MMCS equ 0a6h ; Midrange memory chip select reg.
OFFS_CS_PACS equ 0a4h ; Peripheral chip select register
OFFS_CS_LMCS equ 0a2h ; lmsc register
OFFS_CS_UMCS equ 0a0h ; umcs register
OFFS_CS_IMCS equ 0ach ; Internal Memory Chip Select reg.
;
;
OFFS_SPRT0_BDV equ 088h ; serial port bauddiv reg
OFFS_SPRT0_RX equ 086h ; serial port receive reg
OFFS_SPRT0_TX equ 084h ; serial port transmit reg
OFFS_SPRT0_STAT equ 082h ; serial port status reg
OFFS_SPRT0_CTL equ 080h ; serial port control reg
OFFS_SPRT_BDV equ 088h ; serial port bauddiv reg
OFFS_SPRT_RX equ 086h ; serial port receive reg
OFFS_SPRT_TX equ 084h ; serial port transmit reg
OFFS_SPRT_STAT equ 082h ; serial port status reg
OFFS_SPRT_CTL equ 080h ; serial port control reg
;
; PIO registers
;
OFFS_PIO_DATA1 equ 07ah ; PIO data 1 register
OFFS_PIO_DIR1 equ 078h ; PIO direction 1 register
OFFS_PIO_MODE1 equ 076h ; PIO mode 1 register
OFFS_PIO_DATA0 equ 074h ; PIO data registers
OFFS_PIO_DIR0 equ 072h ; PIO direction register
OFFS_PIO_MODE0 equ 070h ; PIO mode 0 register
;
; Timer 2 control registers
;
OFFS_TMR2_CTL equ 066h ; Timer 2 mode/control register
OFFS_TMR2_MAXA equ 062h ; Timer 2 maxcount compare A register
OFFS_TMR2_CNT equ 060h ; Timer 2 count register
;
; Timer 1 control registers
;
OFFS_TMR1_CTL equ 05eh ; Timer 1 mode/control register
OFFS_TMR1_MAXB equ 05ch ; Timer 1 maxcount compare B register
OFFS_TMR1_MAXA equ 05ah ; Timer 1 maxcount compare A register
OFFS_TMR1_CNT equ 058h ; Timer 1 count register
;
; Timer 0 control registers
;
OFFS_TMR0_CTL equ 056h ; Timer 0 mode/control register
OFFS_TMR0_MAXB equ 054h ; Timer 0 maxcount compare B register
OFFS_TMR0_MAXA equ 052h ; Timer 0 maxcount compare A register
OFFS_TMR0_CNT equ 050h ; Timer 0 count register
;
; Interrupt registers
;
OFFS_INT_SPRT0 equ 044h ; sprt 0 interrupt ctrl reg
OFFS_INT_SPRT equ 044h ; serial port interrupt control reg
OFFS_INT_WDOG equ 042h ; Watchdog timer interrupt control
;
OFFS_INT_INT4 equ 040h ; INT4 control register
OFFS_INT_INT3 equ 03eh ; INT3 control register
OFFS_INT_INT2 equ 03ch ; INT2 control register
OFFS_INT_INT1 equ 03ah ; INT1 control register
OFFS_INT_INT0 equ 038h ; INT0 control register
OFFS_INT_DMA1 equ 036h ; DMA1 interrupt control register
OFFS_INT_DMA0 equ 034h ; DMA0 interrupt control register
OFFS_INT_TMR equ 032h ; Timer interrupt control register
OFFS_INT_STAT equ 030h ; Interrupt status register
OFFS_INT_IREQ equ 02eh ; Interrupt request register
OFFS_INT_INSV equ 02ch ; In-service register
OFFS_INT_PMSK equ 02ah ; Priority mask register
OFFS_INT_MASK equ 028h ; Interrupt mask register
OFFS_INT_PSTT equ 026h ; Poll status register
OFFS_INT_POLL equ 024h ; Poll register
OFFS_INT_EOI equ 022h ; End-of-interrupt register
OFFS_INT_VEC equ 020h ; Interrupt vector register
;
; Synchronous serial port register
;
OFFS_SS_RX equ 018h ; Synchronous serial receive register
OFFS_SS_TX0 equ 016h ; Synchronous serial transmit 0 reg.
OFFS_SS_TX1 equ 014h ; Synchronous serial transmit 1 reg.
OFFS_SS_CTL equ 012h ; Synchronous serial control register
OFFS_SS_STAT equ 010h ; Synchronous serial status register
;
; ======================================================================
; STANDARD EXTERNAL-MEMORY SEGMENT AND OFFSET MAP
CTL_OFF equ 0ff00h ; Ctl reg offset for peripherals
; Miscellaneous control registers
;
RELC_REG equ (CTL_OFF+OFFS_RELC_REG)
RI_REG equ (CTL_OFF+OFFS_RI_REG)
BISTEA_REG equ (CTL_OFF+OFFS_BISTEA_REG)
BISTSC_REG equ (CTL_OFF+OFFS_BISTSC_REG)
RCFG_REG equ (CTL_OFF+OFFS_RCFG_REG)
PRL_REG equ (CTL_OFF+OFFS_PRL_REG)
PDCN_REG equ (CTL_OFF+OFFS_PDCN_REG)
;
; Refresh control unit registers
;
DRAM_ENAB equ (CTL_OFF+OFFS_DRAM_ENAB)
DRAM_CLK equ (CTL_OFF+OFFS_DRAM_CLK)
DRAM_MEM equ (CTL_OFF+OFFS_DRAM_MEM)
;
; DMA 1 registers
;
DMA1_CTL equ (CTL_OFF+OFFS_DMA1_CTL)
DMA1_CNT equ (CTL_OFF+OFFS_DMA1_CNT)
DMA1_DSH equ (CTL_OFF+OFFS_DMA1_DSH)
DMA1_DES equ (CTL_OFF+OFFS_DMA1_DES)
DMA1_SRH equ (CTL_OFF+OFFS_DMA1_SRH)
DMA1_SRC equ (CTL_OFF+OFFS_DMA1_SRC)
;
; DMA 0 registers
;
DMA0_CTL equ (CTL_OFF+OFFS_DMA0_CTL)
DMA0_CNT equ (CTL_OFF+OFFS_DMA0_CNT)
DMA0_DSH equ (CTL_OFF+OFFS_DMA0_DSH)
DMA0_DES equ (CTL_OFF+OFFS_DMA0_DES)
DMA0_SRH equ (CTL_OFF+OFFS_DMA0_SRH)
DMA0_SRC equ (CTL_OFF+OFFS_DMA0_SRC)
;
; Chip select registers
;
CS_MPCS equ (CTL_OFF+OFFS_CS_MPCS)
CS_MMCS equ (CTL_OFF+OFFS_CS_MMCS)
CS_PACS equ (CTL_OFF+OFFS_CS_PACS)
CS_LMCS equ (CTL_OFF+OFFS_CS_LMCS)
CS_UMCS equ (CTL_OFF+OFFS_CS_UMCS)
CS_IMCS equ (CTL_OFF+OFFS_CS_IMCS)
;
; Asynchronous serial port registers
;
SPRT0_BDV equ (CTL_OFF+OFFS_SPRT0_BDV)
SPRT0_RX equ (CTL_OFF+OFFS_SPRT0_RX)
SPRT0_TX equ (CTL_OFF+OFFS_SPRT0_TX)
SPRT0_STAT equ (CTL_OFF+OFFS_SPRT0_STAT)
SPRT0_CTL equ (CTL_OFF+OFFS_SPRT0_CTL)
SPRT_BDV equ (CTL_OFF+OFFS_SPRT_BDV)
SPRT_RX equ (CTL_OFF+OFFS_SPRT_RX)
SPRT_TX equ (CTL_OFF+OFFS_SPRT_TX)
SPRT_STAT equ (CTL_OFF+OFFS_SPRT_STAT)
SPRT_CTL equ (CTL_OFF+OFFS_SPRT_CTL)
;
; PIO registers
;
PIO_DATA1 equ (CTL_OFF+OFFS_PIO_DATA1)
PIO_DIR1 equ (CTL_OFF+OFFS_PIO_DIR1)
PIO_MODE1 equ (CTL_OFF+OFFS_PIO_MODE1)
PIO_DATA0 equ (CTL_OFF+OFFS_PIO_DATA0)
PIO_DIR0 equ (CTL_OFF+OFFS_PIO_DIR0)
PIO_MODE0 equ (CTL_OFF+OFFS_PIO_MODE0)
;
; Timer 2 control registers
;
TMR2_CTL equ (CTL_OFF+OFFS_TMR2_CTL)
TMR2_MAXA equ (CTL_OFF+OFFS_TMR2_MAXA)
TMR2_CNT equ (CTL_OFF+OFFS_TMR2_CNT)
;
; Timer 1 control registers
;
TMR1_CTL equ (CTL_OFF+OFFS_TMR1_CTL)
TMR1_MAXB equ (CTL_OFF+OFFS_TMR1_MAXB)
TMR1_MAXA equ (CTL_OFF+OFFS_TMR1_MAXA)
TMR1_CNT equ (CTL_OFF+OFFS_TMR1_CNT)
;
; Timer 0 control registers
;
TMR0_CTL equ (CTL_OFF+OFFS_TMR0_CTL)
TMR0_MAXB equ (CTL_OFF+OFFS_TMR0_MAXB)
TMR0_MAXA equ (CTL_OFF+OFFS_TMR0_MAXA)
TMR0_CNT equ (CTL_OFF+OFFS_TMR0_CNT)
;
; Interrupt registers
;
INT_SPRT0 equ (CTL_OFF+OFFS_INT_SPRT0)
INT_SPRT equ (CTL_OFF+OFFS_INT_SPRT)
INT_WDOG equ (CTL_OFF+OFFS_INT_WDOG)
;
INT_INT4 equ (CTL_OFF+OFFS_INT_INT4)
INT_INT3 equ (CTL_OFF+OFFS_INT_INT3)
INT_INT2 equ (CTL_OFF+OFFS_INT_INT2)
INT_INT1 equ (CTL_OFF+OFFS_INT_INT1)
INT_INT0 equ (CTL_OFF+OFFS_INT_INT0)
INT_DMA1 equ (CTL_OFF+OFFS_INT_DMA1)
INT_DMA0 equ (CTL_OFF+OFFS_INT_DMA0)
INT_TMR equ (CTL_OFF+OFFS_INT_TMR)
INT_STAT equ (CTL_OFF+OFFS_INT_STAT)
INT_IREQ equ (CTL_OFF+OFFS_INT_IREQ)
INT_INSV equ (CTL_OFF+OFFS_INT_INSV)
INT_PMSK equ (CTL_OFF+OFFS_INT_PMSK)
INT_MASK equ (CTL_OFF+OFFS_INT_MASK)
INT_PSTT equ (CTL_OFF+OFFS_INT_PSTT)
INT_POLL equ (CTL_OFF+OFFS_INT_POLL)
INT_EOI equ (CTL_OFF+OFFS_INT_EOI)
INT_VEC equ (CTL_OFF+OFFS_INT_VEC)
;
; Synchronous serial port register
;
SS_RX equ (CTL_OFF+OFFS_SS_RX)
SS_TX0 equ (CTL_OFF+OFFS_SS_TX0)
SS_TX1 equ (CTL_OFF+OFFS_SS_TX1)
SS_CTL equ (CTL_OFF+OFFS_SS_CTL)
SS_STAT equ (CTL_OFF+OFFS_SS_STAT)
; =======================================================================
; Internal Register field definitions
; RELOCATION REGISTER
REL_REG_SLAVE equ 04000h ; slave interrupt controls
REL_REG_MEMSPACE equ 01000h ; PCB in memory space
; --------------------------------------------------------------
; Processor release level (PRL_REG - offset 0xf4)
PRL_REG_REVA8 equ 02100h ; Am188ER
PRL_REG_REVA6 equ 02000h ; Am186ER
; --------------------------------------------------------------
; Power-save control register (PDCN_REG - offset 0xf0)
PDCN_REG_PSEN equ 08000h ; Power-save enable bit
PDCN_REG_CBF equ 00800h ; CLKOUTB Output Frequency
PDCN_REG_CBD equ 00400h ; CLKOUTB Drive Disable
PDCN_REG_CAF equ 00200h ; CLKOUTA Output Frequency
PDCN_REG_CAD equ 00100h ; CLKOUTA Drive Disable
PDCN_REG_CDIV1 equ 00000h ; clock div factor = 1
PDCN_REG_CDIV2 equ 00001h ; clock div factor = 2
PDCN_REG_CDIV4 equ 00002h ; clock div factor = 4
PDCN_REG_CDIV8 equ 00003h ; clock div factor = 8
PDCN_REG_CDIV16 equ 00004h ; clock div factor = 16
PDCN_REG_CDIV32 equ 00005h ; clock div factor = 32
PDCN_REG_CDIV64 equ 00006h ; clock div factor = 64
PDCN_REG_CDIV128 equ 00007h ; clock div factor = 128
;
; RAM refresh control
;
DRAM_ENABLE equ 08000h ; enable bit for DRAM
INT_INSV_SPRT0 equ 00400h ; serial port 0x
INT_INSV_SPRT1 equ 00200h ; serial port 1
INT_INSV_INT4 equ 00100h ; external int 4
INT_INSV_INT3 equ 00080h ; external int 3
INT_INSV_INT2 equ 00040h ; external int 2
INT_INSV_INT1 equ 00020h ; external int 1
INT_INSV_INT0 equ 00010h ; external int 0x
INT_INSV_DMA1 equ 00008h ; DMA1
INT_INSV_DMA0 equ 00004h ; DMA0
INT_INSV_TMR equ 00001h ; all of the timers (except WDOG)
; -------------------------------------------------------------
; INTERRUPT REQUEST REGISTER BITS (REQST - 0x2e)
INT_REQ_SPRT0 equ INT_INSV_SP0
INT_REQ_SPRT1 equ INT_INSV_SP1
INT_REQ_INT4 equ INT_INSV_INT4
INT_REQ_INT3 equ INT_INSV_INT3
INT_REQ_INT2 equ INT_INSV_INT2
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