sdramcfg.lst

Ep93XX TionProV2 BSP

  108 00000018          ; 
  109 00000018 e3a0010e                 ldr             r0, =(GLOBALCFG_INIT :or: GLOBALCFG_MRS :or:                                       GLOBALCFG_C 
                        KE) 
  111 0000001c e59f10a8                 ldr             r1, =0x80060004 
  112 00000020 e5810000                 str             r0, [r1] 
  113 00000024            
  114 00000024                          Delay200 
  115 00000030            
  116 00000030          ; 
  117 00000030          ; Clear the MRS bit to issue a precharge all. 
  118 00000030          ; 
  119 00000030 e3a00106                 ldr             r0, =(GLOBALCFG_INIT :or: GLOBALCFG_CKE) 
  120 00000034 e5810000                 str             r0, [r1] 
  121 00000038            
  122 00000038          ; 
  123 00000038          ; Accodring to SDRAM errata, precharge all doesn't work. 
  124 00000038          ; Wrokaround is to do four precharge commands. 
  125 00000038          ; Issue precharfe to each SDRAM bank. 
  126 00000038          ; 
  127 00000038 e3a000ff                 mov             r0, #0xff 
  128 0000003c            
  129 0000003c e3a01000                 ldr             r1, =0x0 
  130 00000040 e5810000                 str             r0, [r1] 
  131 00000044            
  132 00000044 e3a01501                 ldr             r1, =0x400000 
  133 00000048 e5810000                 str             r0, [r1] 
  134 0000004c            
  135 0000004c e3a01502                 ldr             r1, =0x800000 
  136 00000050 e5810000                 str             r0, [r1] 
  137 00000054            
  138 00000054 e3a01503                 ldr             r1, =0xc00000 
  139 00000058 e5810000                 str             r0, [r1] 
  140 0000005c            
  141 0000005c          ; 
  142 0000005c          ; Temporarily set the refresh timer to 0x10.  Make it really low so that auto refresh 
  143 0000005c          ; cycles are generated. is refreshed. 
  144 0000005c          ; 
  145 0000005c e3a00010                 ldr             r0, =0x10 
  146 00000060 e59f1068                 ldr             r1, =0x80060008 
  147 00000064 e5810000                 str             r0, [r1] 
  148 00000068            
  149 00000068                          Delay80 
  150 00000074            
  151 00000074 e3a00f81                 ldr             r0, =0x204 
  152 00000078 e59f1050                 ldr             r1, =0x80060008 
  153 0000007c e5810000                 str             r0, [r1] 
  154 00000080            
  155 00000080          ; 
  156 00000080          ; Select mode register update mode 
  157 00000080          ; 
  158 00000080 e3a0010a                 ldr             r0, =(GLOBALCFG_CKE :or: GLOBALCFG_MRS) 
  159 00000084 e59f1040                 ldr             r1, =0x80060004 
  160 00000088 e5810000                 str             r0, [r1] 
  161 0000008c            
  162 0000008c          ; ******************************************************************* 
  163 0000008c          ; 
  164 0000008c          ; Program the SDRAM mode register using the row information. 
  165 0000008c          ; 
  166 0000008c          ;       |           |           |           | 
  167 0000008c          ; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 
  168 0000008c          ; |13|12|11|10|09|08|07|06|05|04|03|02|01|00| 
  169 0000008c          ; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+ 
  170 0000008c          ;   +---------+------+  +---+--+  +   +--+--+ 
  171 0000008c          ;              |             |     |     | 
  172 0000008c          ;          Must Be Zero      |     |     | 
  173 0000008c          ;                            |     |     | 
  174 0000008c          ;                            |     |     | 
  175 0000008c          ;    LTMODE   ---------------+     |     | 
  176 0000008c          ;                                  |     | 
  177 0000008c          ;  Wrap type  ---------------------+     | 
  178 0000008c          ;                                        | 
  179 0000008c          ; CAS Latency ---------------------------+ 
  180 0000008c          ; 
  181 0000008c          ; ******************************************************************* 
  182 0000008c          ; 
  183 0000008c          ; Row Column mapping for 256Meg X 16 Bits X 2. SROM Look Alike mode 
  184 0000008c          ; 
  185 0000008c          ;           B1  B0  A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 
  186 0000008c          ; 
  187 0000008c          ; Row/Bank  A23 A22 A27 A26 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10  
  188 0000008c          ; 
  189 0000008c          ; Col       A23 A22             AP  A25 A24 A09 A08 A07 A06 A05 A04 A03 A02  
  190 0000008c          ; 
  191 0000008c          ; ******************************************************************* 
  192 0000008c          ; Sets all four banks using  - Cas latency 2  
  193 0000008c          ;                            - Wrap type sequential 
  194 0000008c          ;                            - Burst Length 4  
  195 0000008c          ; 
  196 0000008c          ; ******************************************************************* 
  197 0000008c e3a01b22                 ldr             r1, =0x0008800 
  198 00000090 e5910000                 ldr             r0, [r1] 
  199 00000094            
  200 00000094 e59f1038                 ldr             r1, =0x0408800 
  201 00000098 e5910000                 ldr             r0, [r1] 
  202 0000009c            
  203 0000009c e59f1034                 ldr             r1, =0x0808800 
  204 000000a0 e5910000                 ldr             r0, [r1] 
  205 000000a4            
  206 000000a4 e59f1030                 ldr             r1, =0x0C08800 
  207 000000a8 e5910000                 ldr             r0, [r1] 
  208 000000ac            
  209 000000ac          ; 
  210 000000ac          ; Select mode register update mode 
  211 000000ac          ; 
  212 000000ac e3a00102                 ldr             r0, =GLOBALCFG_CKE 
  213 000000b0 e59f1014                 ldr             r1, =0x80060004 
  214 000000b4 e5810000                 str             r0, [r1] 
  215 000000b8            
  216 000000b8          ; 
  217 000000b8          ; Perform a dummy read of memory. 
  218 000000b8          ; 
  219 000000b8 e3a00901                 ldr             r0, =0x00004000 
  220 000000bc e5901000                 ldr             r1, [r0] 
  221 000000c0 e1a0f00e                 mov             pc, lr 
  222 000000c4            
  223 000000c4                          END 
   23 000000c4            
   24 000000c4                  END 
   25 000000c4 00210028 *literal pool: constant 
   25 000000c8 8006001c *literal pool: constant 
   25 000000cc 80060004 *literal pool: constant 
   25 000000d0 80060008 *literal pool: constant 
   25 000000d4 00408800 *literal pool: constant 
   25 000000d8 00808800 *literal pool: constant 
   25 000000dc 00c08800 *literal pool: constant 
Assembly terminated, errors: 0, warnings: 0