sdramcfg.lst

Ep93XX TionProV2 BSP

ARM macroassembler      Page:1 
    1 00000000          ;********************************************************************** 
    2 00000000          ;                                                                       
    3 00000000          ; Filename: sdramcfg.s 
    4 00000000          ;                                                                       
    5 00000000          ; Description: Configure SDRAM 
    6 00000000          ; 
    7 00000000          ; THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF 
    8 00000000          ; ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO 
    9 00000000          ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A 
   10 00000000          ; PARTICULAR PURPOSE. 
   11 00000000          ; 
   12 00000000          ; Use of this source code is subject to the terms of the Cirrus end-user 
   13 00000000          ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT. 
   14 00000000          ; If you did not accept the terms of the EULA, you are not authorized to  
   15 00000000          ; use this source code. For a copy of the EULA, please see the  
   16 00000000          ; EULA.RTF on your install media. 
   17 00000000          ; 
   18 00000000          ; Copyright(c) Cirrus Logic Corporation 2005, All Rights Reserved                        
   19 00000000          ;                                                                       
   20 00000000          ;********************************************************************** 
   21 00000000            
   22 00000000                  INCLUDE ..\..\kernel\hal\edb9307_1x\sdramcfg.s 
    1 00000000          ;********************************************************************** 
    2 00000000          ;                                                                       
    3 00000000          ; Filename: sdramcfg.s 
    4 00000000          ;                                                                       
    5 00000000          ; Description: Configures SDRAM. 
    6 00000000          ; 
    7 00000000          ; THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF 
    8 00000000          ; ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO 
    9 00000000          ; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A 
   10 00000000          ; PARTICULAR PURPOSE. 
   11 00000000          ; 
   12 00000000          ; Use of this source code is subject to the terms of the Cirrus end-user 
   13 00000000          ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT. 
   14 00000000          ; If you did not accept the terms of the EULA, you are not authorized to  
   15 00000000          ; use this source code. For a copy of the EULA, please see the  
   16 00000000          ; EULA.RTF on your install media. 
   17 00000000          ; 
   18 00000000          ; Copyright(c) Cirrus Logic Corporation 2005, All Rights Reserved                        
   19 00000000          ;                                                                       
   20 00000000          ;********************************************************************** 
   21 00000000            
   24 00000000                          OPT     1   ; reenable listing 
   25 00000000                          OPT     128 ; disable listing of macro expansions 
   26 00000000            
   27 00000000          GLOBALCFG_INIT              EQU         0x00000001 
   28 00000000          GLOBALCFG_MRS               EQU         0x00000002 
   29 00000000          GLOBALCFG_SMEMBUSY          EQU         0x00000020 
   30 00000000          GLOBALCFG_LCR               EQU         0x00000040 
   31 00000000          GLOBALCFG_REARBEN           EQU         0x00000080 
   32 00000000          GLOBALCFG_CLKSHUTDOWN       EQU         0x40000000 
   33 00000000          GLOBALCFG_CKE               EQU         0x80000000 
   34 00000000            
   35 00000000            
   36 00000000          REFRESH_MASK                EQU         0x0000FFFF 
   37 00000000            
   38 00000000          BOOTSTATUS_WIDTH_32         EQU         0x00000002 
   39 00000000          BOOTSTATUS_WIDTH_16         EQU         0x00000001 
   40 00000000          BOOTSTATUS_WIDTH_8          EQU         0x00000000 
   41 00000000          BOOTSTATUS_WIDTH_MASK       EQU         0x00000003 
   42 00000000          BOOTSTATUS_MEDIA            EQU         0x00000004 
   43 00000000            
   44 00000000          DEVCFG_EXTBUSWIDTH          EQU         0x00000004 
   45 00000000          DEVCFG_BANKCOUNT            EQU         0x00000008 
   46 00000000          DEVCFG_SROM512              EQU         0x00000010 
   47 00000000          DEVCFG_SROMLL               EQU         0x00000020 
   48 00000000          DEVCFG_2KPAGE               EQU         0x00000040 
   49 00000000          DEVCFG_SFCONFIGADDR         EQU         0x00000080 
   50 00000000          DEVCFG_CASLAT_MASK          EQU         0x00070000 
   51 00000000          DEVCFG_CASLAT_2             EQU         0x00010000 
   52 00000000          DEVCFG_CASLAT_3             EQU         0x00020000 
   53 00000000          DEVCFG_CASLAT_4             EQU         0x00030000 
   54 00000000          DEVCFG_CASLAT_5             EQU         0x00040000 
   55 00000000          DEVCFG_CASLAT_6             EQU         0x00050000 
   56 00000000          DEVCFG_CASLAT_7             EQU         0x00060000 
   57 00000000          DEVCFG_CASLAT_8             EQU         0x00070000 
   58 00000000          DEVCFG_WBL                  EQU         0x00080000 
   59 00000000          DEVCFG_RASTOCAS_MASK        EQU         0x00300000 
   60 00000000          DEVCFG_RASTOCAS_2           EQU         0x00200000 
   61 00000000          DEVCFG_RASTOCAS_3           EQU         0x00300000 
   62 00000000          DEVCFG_AUTOPRECHARGE        EQU         0x01000000 
   63 00000000            
   64 00000000          ;**************************************************************************** 
   65 00000000          ; Delay200 - Delays200 us 
   66 00000000          ; 
   67 00000000          ;  =  200uS / 2 (Instructions/ Loop) * 150 (nS/Instruction) 
   68 00000000          ; 
   69 00000000          ;  =  700 
   70 00000000          ; 
   71 00000000          ;   Uses    r0 
   72 00000000          ;**************************************************************************** 
   73 00000000                          MACRO            
   74 00000000                          Delay200 
   75 00000000                          mov             r0, #700 
   76 00000000          200             subs            r0, r0, #1 
   77 00000000                          bne             %b200 
   78 00000000                          MEND 
   79 00000000            
   80 00000000          ;**************************************************************************** 
   81 00000000          ; Delay80 - Delays 80 Clocks 
   82 00000000          ; 
   83 00000000          ; 
   84 00000000          ;   Uses    r0 
   85 00000000          ;**************************************************************************** 
   86 00000000                          MACRO            
   87 00000000                          Delay80 
   88 00000000                          mov             r0, #80 
   89 00000000          80              subs            r0, r0, #1 
   90 00000000                          bne             %b80 
   91 00000000                          MEND 
   92 00000000            
   93 00000000                          TEXTAREA 
   94 00000000                          EXPORT          SdramCfg 
   95 00000000                          LEAF_ENTRY      SdramCfg 
   96 00000000            
   97 00000000          ; 
   98 00000000          ; Initialize the SDRAM Configuration 
   99 00000000          ; 
  100 00000000 e59f00bc                 ldr             r0, =(DEVCFG_BANKCOUNT :or: DEVCFG_SROMLL :or:                                       DEVCFG_CA 
                        SLAT_2  :or: DEVCFG_RASTOCAS_2 ) 
  102 00000004 e59f10bc                 ldr             r1, =0x8006001C 
  103 00000008 e5810000                 str             r0, [r1] 
  104 0000000c            
  105 0000000c                          Delay200 
  106 00000018          ; 
  107 00000018          ; Set the Initialize and MRS bits (issue continuous NOP commands (INIT & MRS set))