main.c

来自「mpc55**系列芯片的例程 包括SCI,SPI,TIMER,FIT,EDMA」· C语言 代码 · 共 62 行

/*****************************************************************************
 * FILE NAME: main.c                            COPYRIGHT (c) FREESCALE 2006 *
 * DESCRIPTION:                                        All Rights Reserved   *
 * Sample eTPU program based on gpio_example function.                       *
 * Original author:  J. Loelinger, modified by K Terry, G Emerson, S Mihalik *
 * 0.7   S. Mihalik   10/Aug/07    Modified for sysclk = 64 MHz              *
 * 0.8   S. Mihalik   12/May/08    Added options for 40 MHz crystal, MPC563m *
 ****************************************************************************/
/* Notes:  */
/*  1. MMU not initialized; must be done by debug scripts or BAM */
/*  2. SRAM not initialized; must be done by debug scripts or in a crt0 type file */

/* Use one of the next two pairs of lines for header files */
#include "mpc563m.h" /* Use proper include file such as mpc5510.h or mpc5554.h */
#include "mpc563m_vars.h"       /* MPC563m specific variables */
#include "etpu_util.h"          /* useful utility routines */
#include "etpu_set1.h"          /* eTPU standard function set 1 */
#include "etpu_pwm.h"           /* eTPU PWM API */

/* User written include files */
#include "main.h"        /* include application specific defines. */

uint32_t *fs_free_param; /* pointer to the first free parameter */

void initSysclk (void) {
/* MPC563x: Use the next line        */
  FMPLL.ESYNCR1.B.CLKCFG = 0X7;       /* Change clk to PLL normal mode from crystal */  
/* MPC555x including MPC563x: use the next 3 lines for either 8 or 40 MHz crystal */
  FMPLL.SYNCR.R = 0x16080000;         /* 8 MHz xtal: 0x16080000; 40MHz: 0x46100000 */
  while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK  */
  FMPLL.SYNCR.R = 0x16000000;         /* 8 MHz xtal: 0x16000000; 40MHz: 0x46080000 */
}

main ()
{
  int32_t error_code;               /* Returned value from etpu API functions */

  initSysclk();                     /* Initialize PLL to 64 MHz */
                                    /* Initialize eTPU hardware */
  fs_etpu_init (             my_etpu_config, 
                (uint32_t *) etpu_code, 
                             sizeof (etpu_code),
                (uint32_t *) etpu_globals, 
                             sizeof (etpu_globals));
                                    /* Initialize eTPU channel ETPU_A[5] */
  error_code = fs_etpu_pwm_init  (5,    /*  Channel ETPU_A[5] */
                                  FS_ETPU_PRIORITY_MIDDLE,
                                  1000,  /* Frequency = 1000 Hz*/
                                  2500,  /* Duty cycle = 2500/100 = 25% */
                                  FS_ETPU_PWM_ACTIVEHIGH,
                                  FS_ETPU_TCR1,
                                  1000000); /* Timebase (TCR1) freq is 1 MHz */

  SIU.PCR[119].R = 0x0E00;          /* Configure pad for signal ETPU_A[5] output */
  fs_timer_start ();                /* Enable all timebases */
  error_code = fs_etpu_pwm_update (5,     /* Channel ETPU_A[5] */
                                   2000,  /* New frequency = 2KHz	*/
                                   6000,  /* New duty cycle = 6000/100= 60% */
                                   1000000); /* Timebase (TCR1) freq = 1 MHz */

  while(1);                         /* Wait forever */
}