📄 etpuc_spi.c
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/****************************************************************************
* FILE NAME: etpuc_spi.c COPYRIGHT (c) FREESCALE 2004 *
* DESCRIPTION: All Rights Reserved *
* This function uses 3 channels to form a uni or bi directional *
* synchronous serial port that can be used to communicate with a wide *
* variety of devices. *
*==========================================================================*
* $Log: etpuc_spi.c,v $
* Revision 1.3 2004/11/02 15:20:48 r47354
* Add labels to prevent 1.0.0.5 compiler over optimising
*
* Revision 1.2 2004/11/02 14:03:46 r12110
* -Added support for building function stand alone or in a set.
* -This includes using the global error function if avaialable.
* -Updated comments in auto generated file to include version number.
*
* Revision 1.1 2004/11/01 15:50:46 r12110
* No changes to code, just updated for CVS and checked into CVS.
*
*..........................................................................*
* 0.01 J. Scott 25/Mar/04 Initial version of file. *
* J. Scott 06/Apr/04 *
* 0.03 J. Scott 31/May/04 Updated code to MetroWerks for testing *
* 0.04 J. Scott 03/June/04 Updated code to fix a bug with data_reg *
* 0.05 G.Emerson 01/July/04 Fix bug with erta init. Write to erta *
* before switching channels *
* 0.06 G.Emerson 06/July/04 Fix bug with CI/DTR; These are now sent *
* on even edge. *
* Changes for GCT *
* Added disablematches to TCR2 init *
* Changed so that init sends no data *
* Removed data shifting at the end. This *
* will now be done by the host. *
* Add disclaimer *
* 0.07 G.Emerson 19/July/04 Post review changes: *
* Code size optimisations *
* Update comments etc *
* Remove data_out variable *
* Add Global_Error_Func call *
* Add OutputBufferEnable to TX channel *
* 0.08 G.Emerson 17/Aug/04 Fix bug with first clk width *
* 0.09 G.Emerson 10/Sep/04 Fix comment numbering in SPI_RUN_TCR1 *
****************************************************************************/
#ifndef __ETPUC_H
#include <etpuc.h> /*Defines eTPU hardware*/
#endif
#ifndef __ETPUC_COMMON_H
#include <eTPUc_common.h> /*Standard way to use eTPU*/
#endif
/* SPI Definitions */
/* Host Service Requests */
#define SPI_INIT_TCR1 7
#define SPI_INIT_TCR2 5
#define SPI_RUN 3
/* Function Modes */
#define SPI_CLK_POL_POS 0
#define SPI_CLK_POL_NEG 1
#define SPI_SHIFT_DIR_MSB 0
#define SPI_SHIFT_DIR_LSB 1
#ifdef SPI_FUNCTION_NUMBER
#pragma ETPU_function SPI, alternate @ SPI_FUNCTION_NUMBER;
#else
#pragma ETPU_function SPI, alternate;
#endif
/*------------------------------------------------------------------------*/
/* CHANNEL PARAMETERS: (host modifiable) */
/* bit_count: Contains the number of bits to be transferred */
/* Range = 0x01 - 0x18 (1 to 24) */
/* */
/* data_reg: 24-bit register that stores the data transferred in and */
/* out */
/* */
/* half_period: Half Baud rate period. This is calculated in the API. */
/* In the simulator half_period can be changed within the */
/* range of 0x01 - 0x7FFFFF */
/* LOCAL VARIABLES: */
/* bit_count_current: this value will be updated as the no of bits to */
/* be transferred is reduced */
/* FLAGS: */
/* Flag1: Used to signify if the shift direction is MSB or LSB first */
/* Assigned to SPI_SHIFT_DIR_MSB/LSB in init thread */
/* */
/* Odd and even threads */
/* Threads where m1==1 & m2 ==0 are odd threads */
/* Threads where m1==0 & m2 ==1 are even threads */
/* in odd threads the next even event is scheduled (ertb is programmed) */
/* in even threads the next odd event is scheduled (erta is programmed) */
/* An odd event is programmed by the run thread */
/* ______ */
/* | | | */
/* | | | <<<<---CLK */
/* ______| |_______| */
/* I O E O */
/* N D V D -----ETC ETC */
/* I D E D */
/* T N */
/* */
/*------------------------------------------------------------------------*/
void SPI (int8 bit_count, int24 data_reg, int24 half_period)
{
int8 bit_count_current;
/********************************************************************/
/* THREAD NAME : SPI_INIT_TCR1 */
/********************************************************************/
/* 1. Disable Matches during this thread */
/* */
/* 2. Set up to use TCR1 */
/* */
/* 3. Clear flag0 */
/* */
/* 4. Set channel mode : EM_NB_ST */
/* */
/* 5. Set Function Mode (Shift Direction) = Flag 1 */
/* */
/* 6. Clear match and transition Latches */
/* */
/* 7. Set Pin Hi/Low according to Clock Polarity */
/* */
/* 8. Enable the output buffer on the clk channel */
/* */
/* 9. Set Channel interrupt and Data Transfer request bits */
/* */
/* 10. Enable events handling for matches and transitions */
/* */
/* 11. Disable the output buffer on the Rx channel */
/********************************************************************/
if (hsr == SPI_INIT_TCR1)
{
DisableMatchesInThread ();
/* SET UP TO USE TCR1 */
ActionUnitA (MatchTCR1, CaptureTCR1, GreaterEqual);
ActionUnitB (MatchTCR1, CaptureTCR1, GreaterEqual);
flag0 = 0;
Init_SPI:
EitherMatchNonBlockingSingleTransition (); /* SET CHANNEL MODE */
/* SET FUNCTION MODE SHIFT DIRECTION AS FLAG 1 */
flag1 = 1; /* SHIFT MSB FIRST : default*/
if (FunctionMode1 != SPI_SHIFT_DIR_MSB)
{
flag1 = 0; /* SHIFT LSB FIRST */
}
Clear (TransLatch);
ClearMatchAEvent ();
ClearMatchBEvent ();
/* SET PIN HIGH OR LOW ON INITIALISATION */
if (FunctionMode0 == SPI_CLK_POL_POS) /* POLARITY = 0 SO +VE 1ST EDGE */
{
SetPinLow (); /* Ready for 1st -ve edge */
}
else /* POLARITY = 1 SO -VE 1ST EDGE */
{
SetPinHigh (); /* Ready for first +ve edge */
}
/* Enable Output Buffer - for Puma */
EnableOutputBuffer ();
SetChannelInterruptRequest ();
SetDataTransferInterruptRequest ();
/* ENABLE EVENT HANDLING */
EnableMatchAndTransitionEventHandling ();
chan--;
DisableOutputBuffer ();
}
/********************************************************************/
/* THREAD NAME : SPI_INIT_TCR2 */
/********************************************************************/
/* 1. Disable Matches during this thread */
/* */
/* 2. Set up to use TCR2 */
/* */
/* 3. Set flag0 */
/* */
/* 4. Proceed as per Thread SPI_INIT_TCR1 step 4 */
/********************************************************************/
else if (hsr == SPI_INIT_TCR2)
{
DisableMatchesInThread ();
/* SET UP TO USE TCR2 */
ActionUnitA (MatchTCR2, CaptureTCR2, GreaterEqual);
ActionUnitB (MatchTCR2, CaptureTCR2, GreaterEqual);
flag0 = 1;
goto Init_SPI;
}
/****************************************************************/
/* THREAD NAME : SPI_RUN_TCR2 */
/****************************************************************/
/* 1. Disable Matches during this thread */
/* */
/* 2. Set erta to a half_period from now */
/* */
/* 3. proceed as per SPI_RUN_TCR1 step 3. */
/****************************************************************/
else if (hsr == SPI_RUN && flag0 == 1 )
{
DisableMatchesInThread ();
erta = tcr2 + half_period;
goto SPI_RUN0;
}
/****************************************************************/
/* THREAD NAME : SPI_RUN_TCR1 */
/****************************************************************/
/* 1. Disable Matches during this thread */
/* */
/* 2. Set erta to a half_period from now */
/* */
/* 3. Clear match and transition Latches */
/* */
/* 4. Schedule match for half_period from now */
/* */
/* 5. Enable the output buffer on the Tx channel */
/* */
/* 6. Shift data_reg dependant upon shift_dir */
/* */
/* 7. Set pin on chan+1 according to carry flag */
/* */
/* 8. Make bit_count_current = bit_count */
/* */
/* 9. Set Pin Action according to CLK polarity */
/****************************************************************/
else if (hsr == SPI_RUN && flag0 == 0 )
{
DisableMatchesInThread ();
erta = tcr1 + half_period;
SPI_RUN0:
Clear (TransLatch);
ClearMatchAEvent ();
ClearMatchBEvent ();
/* COPY THE ERT TO THE MATCH REG AND SET THE MRLE LATCH */
WriteErtAToMatchAAndEnable ();
No_optimise0: /* this label required to prevent the compiler being over zealous */
chan++;
/* Enable Output Buffer - for Puma */
EnableOutputBuffer ();
if (FunctionMode1 != SPI_SHIFT_DIR_MSB)
{
data_reg >>= 1; /* SHIFT LSB FIRST */
}
else
{
data_reg <<= 1; /* SHIFT MSB FIRST */
}
/* PLACE data_out ON OUTPUT CHANNEL FOR ACCESS ON 1ST CLK EDGE */
if (CC.C != 0)
{
SetPinHigh();
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