main.c

mpc55**系列芯片的例程 包括SCI,SPI,TIMER,FIT,EDMA等几乎所有功能的实现

/* main.c - eMIOS OPWM example */
/* Description:  eMIOS example using Modulus Counter and OPWM modes */
/* Rev 1.0 Sept 9 2004 S.Mihalik */
/* Rev 1.1 April 13 2006 S.M.- corrected GPRE to be div by 12 instead of 13*/
/* Rev 1.2 June 26 1006 S.M. - updated comments & made i volatile uint32_t */
/* Rev 1.3 July 19 2007 SM- Changes for MPC551x, 50 MHz sysclk, Mod Ctr data value*/
/* Rev 1.4 Aug 10 2007 SM - Changed to use sysclk of 64 MHz */
/* Rev 1.5 Jun 04 2008 SM - initSysclk changed for MPC5633M support */
/* Copyright Freescale Semiconductor, Inc. 2007 All rights reserved. */
/* Notes:  */
/*  1. MMU not initialized; must be done by debug scripts or BAM */
/*  2. SRAM not initialized; must be done by debug scripts or in a crt0 type file */

#include "mpc563m.h" /* Use proper include file such as mpc5510.h or mpc5554.h */

void initSysclk (void) {
/* MPC551x: Use the next 6 lines     */
/*  CRP.CLKSRC.B.XOSCEN = 1;         */ /* Enable external oscillator */
/*  FMPLL.ESYNCR2.R = 0x00000006;    */ /* Set ERFD to initial value of 6 */
/*  FMPLL.ESYNCR1.R = 0xF0000020;    */ /* Set CLKCFG=PLL, EPREDIV=0, EMFD=0x20*/
/*  while (FMPLL.SYNSR.B.LOCK != 1) {};*/ /* Wait for PLL to LOCK  */
/*  FMPLL.ESYNCR2.R = 0x00000005;    */ /* Set ERFD to final value for 64 MHz sysclk */
/*  SIU.SYSCLK.B.SYSCLKSEL = 2;      */ /* Select PLL for sysclk */
/* MPC563x: Use the next line        */
  FMPLL.ESYNCR1.B.CLKCFG = 0X7;       /* Change clk to PLL normal mode from crystal */  
/* MPC555x including MPC563x: use the next 3 lines   for either 8 or 40 MHz crystal */
  FMPLL.SYNCR.R = 0x16080000;         /* 8 MHz xtal: 0x16080000; 40MHz: 0x46100000 */
  while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK  */
  FMPLL.SYNCR.R = 0x16000000;         /* 8 MHz xtal: 0x16000000; 40MHz: 0x46080000 */
}

void initEMIOS(void) {
  
  EMIOS.MCR.B.GPRE= 63;     /* Divide 64 MHz sysclk by 63+1 = 64 for 1MHz eMIOS clk*/
  EMIOS.MCR.B.ETB = 0;      /* External time base is disabled; Ch 23 drives ctr bus A */
  EMIOS.MCR.B.GPREN = 1;	/* Enable eMIOS clock */
  EMIOS.MCR.B.GTBE = 1;		/* Enable global time base */
  EMIOS.MCR.B.FRZ = 1;		/* Enable stopping channels when in debug mode */
}

void initEMIOSch23(void) {        /* EMIOS CH 23: Modulus Up Counter */
  EMIOS.CH[23].CADR.R = 999;      /* Period will be 999+1 = 1000 clocks (1 msec) */
/* Use one of the following two lines for mode (Note: some MPC555x devices lack MCB) */
  EMIOS.CH[23].CCR.B.MODE = 0x50; /* MPC551x, MPC563x: Mod Ctr Bufd (MCB) int clk */
/* EMIOS.CH[23].CCR.B.MODE = 0x10;*//* MPC555x: Modulus Counter (MC), internal clock */
  EMIOS.CH[23].CCR.B.BSL = 0x3;	  /* Use internal counter */
  EMIOS.CH[23].CCR.B.UCPRE=0;	  /* Set channel prescaler to divide by 1 */
  EMIOS.CH[23].CCR.B.FREN = 1; 	  /* Freeze channel counting when in debug mode */
  EMIOS.CH[23].CCR.B.UCPREN = 1;  /* Enable prescaler; uses default divide by 1 */
}

void initEMIOSch0(void) {         /* EMIOS CH 0: Output Pulse Width Modulation */
  EMIOS.CH[0].CADR.R = 250;       /* Leading edge when channel counter bus=250*/
  EMIOS.CH[0].CBDR.R = 500;       /* Trailing edge when channel counter bus=500*/
  EMIOS.CH[0].CCR.B.BSL = 0x0;	  /* Use counter bus A (default) */
  EMIOS.CH[0].CCR.B.EDPOL = 1;	  /* Polarity-leading edge sets output/trailing clears*/
/* Use one of the following two lines for mode (Note: some MPC555x devices lack OPWMB) */
  EMIOS.CH[0].CCR.B.MODE = 0x60;   /* MPC551x, MPC563x: Mode is OPWM Buffered */
/* EMIOS.CH[0].CCR.B.MODE = 0x20;*//* MPC555x: Mode is OPWM */
/* Use one of the following 2 lines: */
/* SIU.PCR[32].R = 0x0600; */     /* MPC551x: Initialize pad for eMIOS chan. 0 output */
  SIU.PCR[179].R = 0x0E00;        /* MPC555x: Initialize pad for eMIOS chan. 0 output */
}

void initEMIOSch2(void) {         /* EMIOS CH 2: Output Pulse Width Modulation */
  EMIOS.CH[2].CADR.R = 500;       /* Leading edge when channel counter bus=250*/
  EMIOS.CH[2].CBDR.R = 999;       /* Trailing edge when channel counter bus=500*/
  EMIOS.CH[2].CCR.B.BSL = 0x0;	  /* Use counter bus A (default) */
  EMIOS.CH[2].CCR.B.EDPOL = 1;	  /* Polarity-leading edge sets output/trailing clears*/
/* Use one of the following two lines for mode (Note: some MPC555x devices lack OPWMB) */
  EMIOS.CH[2].CCR.B.MODE = 0x60;   /* MPC551x, MPC563x: Mode is OPWM Buffered */
/* EMIOS.CH[2].CCR.B.MODE = 0x20;*//* MPC555x: Mode is OPWM */
/* Use one of the following 2 lines: */
/* SIU.PCR[33].R = 0x0600; */     /* MPC551x: Initialize pad for eMIOS chan. 2 output */
  SIU.PCR[181].R = 0x0E00;        /* MPC555x: Initialize pad for eMIOS chan. 2 output */

}
 
void main (void) {	
  volatile uint32_t i = 0; /* Dummy idle counter */
  
  initSysclk();      /* Set sysclk = 50MHz running from PLL */
  initEMIOS();		 /* Initialize eMIOS to provide 1 MHz clock to channels */
  initEMIOSch23();   /* Initialize eMIOS channel 23 as modulus counter*/
  initEMIOSch0();	 /* Initialize eMIOS channel 0 as OPWM, using ch 23 as time base */
  initEMIOSch2();	 /* Initialize eMIOS channel 2 as OPWM, using ch 23 as time base */
  while (1) {i++; }  /* Wait forever */	
}