main.c

mpc55**系列芯片的例程 包括SCI,SPI,TIMER,FIT,EDMA等几乎所有功能的实现

/* main.c - PLL-sysclk example for MPc563x */
/* Description:  Set PLL to run at 64 MHz based on 8 MHz crystal */
/*               For testing devices without CLKOUT, an eMIOS channel is used */
/* Copyright Freescale Semiconductor, 2008.  All rights reserved. */
/* Rev 1.0 Jul 12 2007 SM- Initial version */
/* Rev 1.1 Aug 14 2007 SM -Changed sysclk to 64 MHz */
/* Rev 1.2 Apr 30 2008 SM- Modified for MPC563x including adding EMIOS OPWFM output*/
/* Notes:  */
/*  1. MMU not initialized; must be done by debug scripts or BAM */
/*  2. L2SRAM not initialized; must be done by debug scripts or in a crt0 type file*/

#include "mpc563m.h" 		/* Used for MPC563m devices */

void initEMIOS(void) {
  
  EMIOS.MCR.B.GPRE= 0x3;	/* eMIOS clk= sysclk/(GPRE+1)= sysclk/4 */
  EMIOS.MCR.B.ETB = 0;      /* Ext. time base is disabled; Ch 23 drives ctr bus A */
  EMIOS.MCR.B.GPREN = 1;	/* Enable eMIOS clock */
  EMIOS.MCR.B.FRZ = 0;		/* Disable freezing channel counters in debug mode */
}

void initEMIOSch12(void) {    /* EMIOS CH 12:Output Pulse Width & Freq Modl'n Buf*/
                              /* Period = 4 emios clks, Duty = 2 eMIOS clks */
                              /* If  8MHz sysclk, Freq= 8MHz/4/4 = 500Kz (2us per.)*/
                              /* If 64MHz sysclk, Freq= 64MHz/4/4= 4MHz (250ns per.)*/
  EMIOS.CH[12].CBDR.R = 4;    /* Period= 4 emios clocks= 16 sysclks */
                              /*         (32usec,4usec for 8M,64Msysclk) */
  EMIOS.CH[12].CADR.R = 3;      /* Duty cycle in emios clks */
  EMIOS.CH[12].CCR.B.UCPRE = 0; /* Channel counter uses divide by (0+1) prescaler */
  EMIOS.CH[12].CCR.B.UCPREN = 1;/* Channel counter's prescaler is loaded & enabled*/ 
  EMIOS.CH[12].CCR.B.EDPOL = 1;	/* Polarity is active high */
  EMIOS.CH[12].CCR.B.MODE= 0x58;/* Mode= 0PWFMB, flag on B match*/
  SIU.PCR[191].B.PA = 1;        /* Initialize pad for eMIOS channel. */
  SIU.PCR[191].B.OBE = 1;       /* Initialize pad for output */
 }
 
void main (void) {	
  volatile uint32_t i=0;              /* Dummy idle counter */
 
  initEMIOS();		    /* Init. eMIOS to provide sysclk/4 to eMIOS channels */
  initEMIOSch12();	    /* Init. eMIOS channel 12 for sysclk/16 OPWFMB */
  EMIOS.MCR.B.GTBE = 1; /* Start timers/counters by enabling global time base */

  SIU.ECCR.B.EBDF = 3;                /* Divide sysclk by 3+1 for CLKOUT */
  FMPLL.ESYNCR1.B.CLKCFG = 0X7;       /* Change clk to PLL normal mode from crystal */  
  FMPLL.SYNCR.R = 0x16080000;         /* Initial values: PREDIV=1, MFD=12, RFD=1 */
  while (FMPLL.SYNSR.B.LOCK != 1) {}; /* Wait for FMPLL to LOCK  */
  FMPLL.SYNCR.R = 0x16000000;         /* Final value for 64 MHz: RFD=0 */

  while (1) { i++; }                  /* Loop forever */
}