audio_test.c

ADI Blackfin BF51X 範例程式

/*******************************************************************
Analog Devices, Inc. All Rights Reserved.

This software is proprietary and confidential.  By using this software
you agree to the terms of the associated Analog Devices License Agreement.

Project Name:  	Power_On_Self_Test

Hardware:		ADSP-BF518F EZ-Board

Description:	This file tests the audio codec on the EZ-Board.
*******************************************************************/


/*******************************************************************
*  include files
*******************************************************************/
#include <sysreg.h>
#include <ccblkfn.h>
#include <signal.h>
#include <complex.h>
#include <math.h>
#include <stdlib.h>
#include <stdio.h>
#include <filter.h>
#include <vector.h>

#include "post_common.h"
#include "Timer_ISR.h"


/*******************************************************************
*  global variables and defines
*******************************************************************/
#define LEFT_LINE_IN					0x0000
#define RIGHT_LINE_IN					0x0200
#define LEFT_HEADPHONE_OUT  			0x0400
#define RIGHT_HEADPHONE_OUT 			0x0600
#define ANALOG_AUDIO_PATH_CONTROL 		0x0800
#define DIGITAL_AUDIO_PATH_CONTROL 		0x0a00
#define POWER_DOWN_CONTROL 				0x0c00
#define DIGITAL_AUDIO_INTERFACE_FORMAT 	0x0e00
#define SAMPLING_CONTROL 				0x1000
#define ACTIVE_CONTROL 					0x1200
#define RESET_CONTROL 					0x1E00

/* names for slots in codec audio frame */
#define INTERNAL_ADC_L0			0
#define INTERNAL_ADC_R0			1

#define INTERNAL_DAC_L0			0
#define INTERNAL_DAC_R0			1

#define INTERNAL_ADC_L1			2
#define INTERNAL_ADC_R1			3

#define INTERNAL_DAC_L1			2
#define INTERNAL_DAC_R1			3

/* size of array sCodecTxRegs */
#define CODEC_REGS_LENGTH	9

/* SPI transfer mode */
#define TIMOD_DMA_TX 0x0003

#define delay 0xf00

/* SPORT0 word length */
#define SLEN_32	0x001f
#define SLEN_16	0x000f

/* DMA flow mode */
#define FLOW_1	0x1000

int iChannel0LeftIn, iChannel1LeftIn;		/* left input data */
int iChannel0RightIn, iChannel1RightIn;		/* right input data */
int iChannel0LeftOut, iChannel1LeftOut;		/* left ouput data */
int iChannel0RightOut, iChannel1RightOut;	/* right ouput data */

volatile short sCodecResetReg = 0x1E00;
volatile short sCodecTxRegs[CODEC_REGS_LENGTH] =
{
	LEFT_LINE_IN					| 0x01b,	/* greater than 0db volume */
	RIGHT_LINE_IN					| 0x01b,	/* greater than 0db volume */
	LEFT_HEADPHONE_OUT				| 0x079,
	RIGHT_HEADPHONE_OUT				| 0x079,
	ANALOG_AUDIO_PATH_CONTROL		| 0x010,
	DIGITAL_AUDIO_PATH_CONTROL		| 0x000,
	POWER_DOWN_CONTROL				| 0x000,
	DIGITAL_AUDIO_INTERFACE_FORMAT	| 0x042,
	SAMPLING_CONTROL				| 0x001,	/* set USB mode */
};

volatile short sCodecActCtl[] =
{
	ACTIVE_CONTROL					| 0x001, 	/* last register write to activate the codec */
};


int iTxBuffer1[4];	/* SPORT0 DMA transmit buffer */
int iRxBuffer1[4];	/* SPORT0 DMA receive buffer */


/* test paramaters */
#define MAX_SAMPLES	 				256
#define REQUIRED_SAMPLES			((MAX_SAMPLES) * 250)
#define DESIRED_FREQ 				((float)3000.0)
#define SAMPLE_RATE 				((float)48000.0)
#define AMPLITUDE					((float)32767)
#define PI							((float)3.141592765309)

#define ACCEPTABLE_DEVIATION_PCT	((float)0.015)
#define ACCEPTABLE_DEVIATION		(DESIRED_FREQ * ACCEPTABLE_DEVIATION_PCT)
#define MAX_DESIRED_FREQ			(DESIRED_FREQ + ACCEPTABLE_DEVIATION)
#define MIN_DESIRED_FREQ			(DESIRED_FREQ - ACCEPTABLE_DEVIATION)
#define MIN_SIGNAL_STRENGTH			(float)35.0
#define MAX_NOISE_THRESHOLD			(float)18.0

volatile int  g_iSampleIndex = 1;
volatile int  g_iSampleCount = 0;
volatile int  g_iIndex = 0;

short *g_fSineWaveIn_Left;
short *g_fSineWaveIn_Right;
short *g_sInput;

bool bMicInLineOut = false;

/*******************************************************************
*  function prototypes
*******************************************************************/
static void Init_Codec(void);
static void Init_Sport0(void);
static void Init_DMA(void);
static void Init_Interrupts(void);
static void Init_Flags(void);
EX_INTERRUPT_HANDLER(Sport0_RX_ISR);
static int Test_Channel(short* psRealIn);
int TEST_AUDIO(void);


/****************************************************************************
*   Function:    Init_Flags
*   Description: Configure PORTG and PORTH flags to control CODEC 
******************************************************************************/
void Init_Flags(void)
{
	/* SPI SCK, SPI MISO, SPI MOSI, DT0PRI, DROPRI, RFS0, RSCLK0, TSCLK0, TFS0*/
	*pPORTG_MUX = 0x0000;
	ssync();

    *pPORTG_FER = PG3 | PG4 | PG5 | PG6 | PG7 | PG8 | PG12 | PG13 | PG14;
	ssync();

	/* SPI SEL 3 */
	*pPORTH_MUX = 0x0008;
	ssync();
	*pPORTH_FER = PH4;
	ssync();
}


/****************************************************************************
*   Function:    Init_Interrupts
*   Description: Init Sport 0 interrupt
******************************************************************************/
void Init_Interrupts(void)
{
	/* assign ISRs to interrupt vectors, sport0 RX ISR -> IVG 9 */
	register_handler(ik_ivg9, Sport0_RX_ISR);

	/* enable Sport0 RX interrupt */
	*pSIC_IMASK0 |= 0x00010000;
}


/****************************************************************************
*   Function:    Init_Codec
*   Description: This function sends all values in the array sCodecResetReg[]
* 				 to the codec. Different configurations can	be set up by
* 				 modifiying the values in this array.
******************************************************************************/
void Init_Codec(void)
{
	int i;
	int j;
	static unsigned char ucActive_LED = 0x01;
	short stat1, stat2;
	bool do_poll = true;

	
	*pSPI0_FLG |= FLS3;							/* enable FLS5 */
	*pSPI0_BAUD = 10;							/* set baud rate: SCK/(2*SPIBAUD) */
	
	/*** first reset the codec ********************************/
	
	*pSPI0_CTL =0x0;								/* configure spi port */	
	*pSPI0_CTL |= TIMOD_DMA_TX | SIZE | MSTR;	/* SPI DMA WR, 16-bit, MSB first, SPI master */	
	*pDMA7_PERIPHERAL_MAP	= 0x7000;			/* set up DMA to transmit, map DMA to SPI */

	/* configure DMA */
	*pDMA7_CONFIG = WDSIZE_16;					/* 16-bit transfers */
	*pDMA7_START_ADDR = (void *)&sCodecResetReg;/* start address of data buffer */
	*pDMA7_X_COUNT = 1;							/* DMA inner loop count */
	*pDMA7_X_MODIFY = 2;						/* inner loop address increment */

	*pDMA7_CONFIG = (*pDMA7_CONFIG | DMAEN);	/* enable DMAs */
	*pSPI0_CTL = (*pSPI0_CTL | SPE);				/* enable SPI */

	/* wait until dma transfers for spi are finished */
	for (j=0; j<0xffff; j++) asm("nop;");

	/*** now setup the other registers ************************/
	
	*pSPI0_CTL = 0x0000;							/* disable SPI */	
	*pSPI0_CTL |= TIMOD_DMA_TX | SIZE | MSTR;	/* SPI DMA WR, 16-bit, MSB first, SPI master */
	*pDMA7_PERIPHERAL_MAP	= 0x7000;			/* set up DMA to transmit, map DMA to SPI */

	/* configure DMA */
	*pDMA7_CONFIG = WDSIZE_16;					/* 16-bit transfers */
	*pDMA7_START_ADDR = (void *)sCodecTxRegs;	/* start address of data buffer */
	*pDMA7_X_COUNT =
		(sizeof(sCodecTxRegs))/(sizeof(short));	/* DMA inner loop count */
	*pDMA7_X_MODIFY = 2;						/* inner loop address increment */
	
	*pDMA7_CONFIG = (*pDMA7_CONFIG | DMAEN);	/* enable DMAs */
	*pSPI0_CTL = (*pSPI0_CTL | SPE);				/* enable SPI */

	/* wait until dma transfers for spi are finished but we also have to give extra 
	   time for the codec to charge:
	
		- Writing 0x0 to POWER_DOWN_CONTROL internally powers the codec and it begins
		  to charge to AVDD/2.
		- We cannot write 0x1 to ACTIVE_CONTROL until the codec is charged over 10% of
		  AVDD or else the codec may not work properly.
		- The charge time is based on the internals of the codec and is calculated as
		  follows: T = C*25K/3.5, where C is the capacitor value on VMID.  The EZ-KIT
		  uses C = 10.1 uF, so our expected charge time is T = (10.1 uF)*(25K)/3.5
		  which equals 72ms.
		- So we must delay at least 72ms before setting the ACTIVE_CONTROL register
	*/
	
	for (j=0; j<0xffffff; j++) asm("nop;");

	/*** lastly activate the digital engine *******************/
	
	*pSPI0_CTL = 0x0000;							/* disable SPI */	
	*pSPI0_CTL |= TIMOD_DMA_TX | SIZE | MSTR;	/* SPI DMA WR, 16-bit, MSB first, SPI master */
	*pDMA7_PERIPHERAL_MAP	= 0x7000;			/* set up DMA to transmit, map DMA to SPI */

	/* configure DMA */
	*pDMA7_CONFIG = WDSIZE_16;					/* 16-bit transfers */
	*pDMA7_START_ADDR = (void *)sCodecActCtl;	/* start address of data buffer */
	*pDMA7_X_COUNT = 1;							/* DMA inner loop count */
	*pDMA7_X_MODIFY = 2;						/* inner loop address increment */
	
	*pDMA7_CONFIG = (*pDMA7_CONFIG | DMAEN);	/* enable DMAs */
	*pSPI0_CTL = (*pSPI0_CTL | SPE);				/* enable SPI */

	/* wait until dma transfers for spi are finished */
	for (j=0; j<0xaff0; j++) asm("nop;");
	
	/**********************************************************/

	*pSPI0_CTL = 0x0000;							/* disable SPI */
}


/****************************************************************************
*   Function:    Init_Sport0
*   Description: Configure SPORT0 for I2S mode, to transmit/receive data
*                to/from the codec. Configure Sport for ext clock and
*                internal frame sync.
******************************************************************************/
void Init_Sport0(void)
{
	/* sport0 receive configuration */
	*pSPORT0_RCR1 = RFSR | RCKFE;
	*pSPORT0_RCR2 = SLEN_32 | RSFSE;

	/* sport0 transmit configuration */
	*pSPORT0_TCR1 = TFSR | TCKFE;
	*pSPORT0_TCR2 = SLEN_32 | TSFSE;

}


/****************************************************************************
*   Function:    Init_DMA
*   Description: DMA Controller Programming For SPORT0
*                Sets up DMA0 and DMA1 in autobuffer mode to receive and
*				 transmit SPORT data
******************************************************************************/
void Init_DMA(void)
{
	/* configure DMA3 */
	
	/* 32-bit transfers, interrupt on completion, autobuffer mode */
	*pDMA3_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
	
	*pDMA3_START_ADDR = iRxBuffer1;		/* start address of data buffer */
	*pDMA3_X_COUNT = 4;					/* DMA loop count */
	*pDMA3_X_MODIFY = 4;				/* DMA loop address increment */