ethernet.c

uCOS-II V2.84 LM3S6965 TCPIP Demo

    //
    // Return the availability of packets.
    //
    return((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR) ? true : false);
}

//*****************************************************************************
//
//! Check for packet space available in the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! The Ethernet Controller's transmit FIFO is designed to support a single
//! packet at a time.  After the packet has been written into the FIFO, the
//! transmit request bit must be set to enable the transmission of the packet.
//! Only after the packet has been transmitted can a new packet be written
//! into the FIFO.  This function will simply check to see if a packet is
//! in progress.  If so, there is no space available in the transmit FIFO.
//!
//! \return This function will return \b true if a space is available in the
//! transmit FIFO, otherwise, will return \b false.
//
//*****************************************************************************
tBoolean
EthernetSpaceAvail(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Return the availability of space.
    //
    return((HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX) ? false : true);
}

//*****************************************************************************
//
//! Receives a packet from the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucBuf is the pointer to the packet buffer.
//! \param lBufLen is the maximum number of bytes to be read into the buffer.
//!
//! This function reads a packet from the receive FIFO of the controller and
//! places it into \e pucBuf.  If no packet is available the function will
//! return immediately.  Otherwise the function will read the entire
//! packet from the receive FIFO.  If there are more bytes in the packet than
//! will fit into \e pucBuf (as specified by \e lBufLen), the function will
//! return the negated length of the packet and the buffer will contain \e
//! lBufLen bytes of the packet.  Otherwise, the function will return the
//! length of the packet that was read and \e pucBuf will contain the entire
//! packet (excluding the frame check sequence bytes).
//!
//! \note This function will return immediately if no packet is available.
//!
//! \return This function will return \b 0 if no packet is available.  If
//! the packet is too large for \e pucBuf, the function will return the
//! negated length \b -n.  Otherwise, the function will return the length
//! \b n of the received packet.
//
//*****************************************************************************
long
EthernetPacketNonBlockingGet(unsigned long ulBase, unsigned char *pucBuf,
                             long lBufLen)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucBuf != 0);
    ASSERT(lBufLen > 0);

    //
    // Check to see if any packets are available.
    //
    if((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR) == 0)
    {
        return(0);
    }

    //
    // Read the packet, and return.
    //
    return(EthernetInternalGetPacket(ulBase, pucBuf, lBufLen));
}

//*****************************************************************************
//
//! Waits for a packet from the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucBuf is the pointer to the packet buffer.
//! \param lBufLen is the maximum number of bytes to be read into the buffer.
//!
//! This function reads a packet from the receive FIFO of the controller and
//! places it into \e pucBuf.  The function will wait until a packet is
//! available in the FIFO.  Then the function will read the entire packet
//! from the receive FIFO.  If there are more bytes in the packet than will
//! fit into \e pucBuf (as specified by \e lBufLen), the function will return
//! the negated length of the packet and the buffer will contain \e lBuflen
//! bytes of the packet.  Otherwise, the function will return the length of
//! the packet that was read and \e pucBuf will contain the entire packet
//! (excluding the frame check sequence bytes).
//!
//! \note This function is blocking, and will not return until a packet
//! arrives.
//!
//! \return If the packet is too large for \e pucBuf, the function will return
//! the negated length \b -n.  Otherwise, the function will return the length
//! \b n of the received packet.
//
//*****************************************************************************
long
EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf,
                  long lBufLen)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucBuf != 0);
    ASSERT(lBufLen > 0);

    //
    // Wait for a packet to become available
    //
    while((HWREG(ulBase + MAC_O_NP) & MAC_NP_NPR) == 0)
    {
    }

    //
    // Read the packet
    //
    return(EthernetInternalGetPacket(ulBase, pucBuf, lBufLen));
}

//*****************************************************************************
//
//! Sends a packet to the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucBuf is the pointer to the packet buffer.
//! \param lBufLen is number of bytes in the packet to be transmitted.
//!
//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
//! into the transmit FIFO of the controller and then activates the
//! transmitter for this packet.  If no space is available in the FIFO, the
//! function will return immediately.  If space is available, the
//! function will return once \e lBufLen bytes of the packet have been placed
//! into the FIFO and the transmitter has been started.  The function will not
//! wait for the transmission to complete.  The function will return the
//! negated \e lBuflen if the length is larger than the space available in
//! the transmit FIFO.
//!
//! \note This function does not block, and will return immediately if no
//! space is available for the transmit packet.
//!
//! \return This function will return \b 0 if no space is available in the
//! transmit FIFO.  If the packet is too large for FIFO, the function will
//! return the negated length \b -lBufLen.  Otherwise, the function will return
//! the length \b lBufLen of the transmitted packet.
//
//*****************************************************************************
long
EthernetPacketNonBlockingPut(unsigned long ulBase, unsigned char *pucBuf,
                             long lBufLen)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucBuf != 0);
    ASSERT(lBufLen > 0);

    //
    // Check if the transmit FIFO is in use and return the appropriate code.
    //
    if(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
    {
        return(0);
    }

    //
    // Send the packet and return.
    //
    return(EthernetInternalPutPacket(ulBase, pucBuf, lBufLen));
}

//*****************************************************************************
//
//! Waits to send a packet from the Ethernet Controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucBuf is the pointer to the packet buffer.
//! \param lBufLen is number of bytes in the packet to be transmitted.
//!
//!
//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
//! into the transmit FIFO of the controller and then activates the
//! transmitter for this packet.  This function will wait until the transmit
//! FIFO is empty.  Once space is available, the function will return once
//! \e lBufLen bytes of the packet have been placed into the FIFO and the
//! transmitter has been started.  The function will not wait for the
//! transmission to complete.  The function will return the negated \e lBuflen
//! if the length is larger than the space available in the transmit FIFO.
//!
//! \note This function blocks, and will wait until space is available for the
//! transmit packet before returning.
//!
//! \return If the packet is too large for FIFO, the function will return the
//! negated length \b -lBufLen.  Otherwise, the function will return the length
//! \b lBufLen of the transmitted packet.
//
//*****************************************************************************
long
EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
                  long lBufLen)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucBuf != 0);
    ASSERT(lBufLen > 0);

    //
    // Wait for current packet (if any) to complete.
    //
    while(HWREG(ulBase + MAC_O_TR) & MAC_TR_NEWTX)
    {
    }

    //
    // Send the packet and return.
    //
    return(EthernetInternalPutPacket(ulBase, pucBuf, lBufLen));
}

//*****************************************************************************
//
//! Registers an interrupt handler for an Ethernet interrupt.
//!
//! \param ulBase is the base address of the controller.
//! \param pfnHandler is a pointer to the function to be called when the
//! enabled Ethernet interrupts occur.
//!
//! This function does the actual registering of the interrupt handler.  This
//! will enable the global interrupt in the interrupt controller; specific
//! Ethernet interrupts must be enabled via EthernetIntEnable().  It is the
//! interrupt handler's responsibility to clear the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pfnHandler != 0);

    //
    // Register the interrupt handler.
    //
    IntRegister(INT_ETH, pfnHandler);

    //
    // Enable the Ethernet interrupt.
    //
    IntEnable(INT_ETH);
}

//*****************************************************************************
//
//! Unregisters an interrupt handler for an Ethernet interrupt.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function does the actual unregistering of the interrupt handler.  It
//! will clear the handler to be called when an Ethernet interrupt occurs.
//! This will also mask off the interrupt in the interrupt controller so that
//! the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetIntUnregister(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Disable the interrupt.
    //
    IntDisable(INT_ETH);

    //
    // Unregister the interrupt handler.
    //
    IntUnregister(INT_ETH);
}

//*****************************************************************************
//
//! Enables individual Ethernet interrupt sources.
//!
//! \param ulBase is the base address of the controller.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated Ethernet interrupt sources.  Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The parameter \e ulIntFlags is the logical OR of any of the following:
//!
//! - ETH_INT_PHY - An interrupt from the PHY has occurred.  The integrated
//!     PHY supports a number of interrupt conditions.  The PHY register,
//!     PHY_MR17, must be read to determine which PHY interrupt has occurred.
//!     This register can be read using the \e EthernetPHYRead() API function.
//! - ETH_INT_MDIO - This interrupt indicates that a transaction on the
//!     management interface has completed successfully.
//! - ETH_INT_RXER - This interrupt indicates that an error has occurred
//!     during reception of a frame.  This error can indicated a length
//!     mismatch, a CRC failure, or an error indication from the PHY.
//! - ETH_INT_RXOF - This interrupt indicates that a frame has been received
//!     that exceeds the available space in the RX FIFO.
//! - ETH_INT_TX - This interrupt indicates that the packet stored in the TX
//!     FIFO has been successfully transmitted.
//! - ETH_INT_TXER - This interrupt indicates that an error has occurred
//!     during the transmission of a packet.  This error can be either a
//!     retry failure during the backoff process, or an invalid length stored
//!     in the TX FIFO.
//! - ETH_INT_RX - This interrupt indicates that one (or more) packets are
//!     available in the RX FIFO for processing.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
                ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));

    //
    // Enable the specified interrupts.
    //
    HWREG(ulBase + MAC_O_IM) |= ulIntFlags;
}

//*****************************************************************************
//
//! Disables individual Ethernet interrupt sources.
//!
//! \param ulBase is the base address of the controller.
//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated Ethernet interrupt sources.  Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//!
//! The parameter \e ulIntFlags has the same definition as the same parameter
//! to EthernetIntEnable().
//!
//! \return None.
//
//*****************************************************************************
void
EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(ulIntFlags & ~(ETH_INT_PHY | ETH_INT_MDIO | ETH_INT_RXER |
                ETH_INT_RXOF | ETH_INT_TX | ETH_INT_TXER | ETH_INT_RX));

    //
    // Disable the specified interrupts.
    //
    HWREG(ulBase + MAC_O_IM) &= ~(ulIntFlags);
}

//*****************************************************************************
//
//! Gets the current Ethernet interrupt status.
//!
//! \param ulBase is the base address of the controller.
//! \param bMasked is false if the raw interrupt status is required and true
//! if the masked interrupt status is required.
//!
//! This returns the interrupt status for the Ethernet Controller.  Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! values described in EthernetIntEnable().
//
//*****************************************************************************
unsigned long
EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
{
    unsigned long ulStatus;