drv_irda.h

sparc硬件平台上的红外驱动

/*********************************************************************
*                
* Filename:      dtk-irda.h  第二次精简的
* Version:       0.1
* Description:   Definitions for the dtk irda driver
* Status:        Experimental.
* Author:        wanax <[e-mail]>
* Created at:    Thu Otc 25 15:37:40 2007
* Modified at:   
* Modified by:        
*     
*     All Rights Reserved
*      
*     This program is free software; you can redistribute it and/or 
*     modify it under the terms of the GNU General Public License as 
*     published by the Free Software Foundation; either version 2 of 
*     the License, or (at your option) any later version.
*  
*     You should have received a copy of the GNU General Public License along with
*     this program; if not, write to the Free Software Foundation, Inc.,
*     59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*     
********************************************************************/


#ifndef  DTK_IRDA_H
#define  DTK_IRDA_H

#include "../../service/irda/netdevice.h"
#include "../../service/irda/irda_device.h"
#include "../../service/irda/irlap.h"
#include "../../service/irda/qos.h"

#include "../../service/irda/types.h"
#include "../../service/irda/skbuff.h"
#include "../../public/pub_emmi.h"
#include "../../kernel/kern_irq.h"
#include "../../service/irda/irda.h"



/* Register  */
#define MCTR 0x08   /* Master Control Register */
#define RBR  0x00   /* Receiver Buffer Register */
#define THR  0x00   /* Transmitter Holding Register */
#define IER   0x01   /* Interrupt Enable Register  RESET VALUE:0000h*/
#define IIR    0x02   /* Interrupt Identification Register */
#define FCR   0x02   /* FIFO Control Register  */
#define LCR   0x03   /* Line Control Register */
#define MCR   0x04  /* Modem Control Register ,ignore this register in irda */
#define LSR   0x05   /* Line Status Register */
#define MSR  0x06   /*  Modem status register ,ignore this register in irda */
#define DLB1 0x00   /* divisor latch byte 1 */
#define DLB2 0x01   /* divisor latch byte 2 */
#define DLB3 0x04   /* divisor latch byte 3 */
#define DLB4 0x05   /* divisor latch byte 4 */

/*
* These are the definitions for the Master Control Register
*/
#define MCTR_MODE_TORR 0x02 /*  1)transmit mode  0) receive mode */
#define MCTR_LOOPBACK 0x04  /* loopback */
#define MCTR_SIR  0x00 /* master low speed  */
#define MCTR_FIR  0x08 /* master high speed  */
#define MCTR_HMIR  0x10 /* master half medium speed  */
#define MCTR_FMIR  0x18 /* master full medium speed  */
#define MCTR_DMA 0x80 /* use dma for data transmission */

/*
* These are the definitions for the Interrupt Enable Register
*/

#define IER_RDAI 0x01  /* enable received data available interrupt */
#define IER_THREI 0x02 /* enable transmitter holding register empty interrupt */
#define IER_RLSI 0x04 /* enable receiver line status interrupt */
#define IER_MSI 0x08 /* enable modem status interrupt */

/*
* These are the definitions for the Interrupt Identification Register
*/
#define IIR_NO_INT	0x01	/* no interrupt is pending */
#define IIR_ID	0x0e	/* mask for the interrupt ID */
#define IIR_MSI	0x00	/* modem status interrupt */
#define IIR_THRI	0x02	/* transmitter holding register empty */
#define IIR_RDI	0x04	/* receiver data interrupt */
#define IIR_RLSI	0x06	/* receiver line status interrupt */
#define IIR_TOI  0x0c  /* timeout indication */

/*
* These are the definitions for the FIFO Control Register
*/
#define FCR_FIFO_EN     0x01 /* Enable FIFO's ,ignore*/
#define FCR_RXSR        0x02 /* Rx FIFO soft reset */
#define FCR_TXSR        0x04 /* Tx FIFO soft reset */
/* define the receiver FIFO Interrupt trigger level */
#define FCR_R_TRIGGER_1        0x00 /* 1 byte  */
#define FCR_R_TRIGGER_4        0x40 /*  4bytes  */
#define FCR_R_TRIGGER_8        0x80 /*  8bytes  */
#define FCR_R_TRIGGER_14       0xc0 /*  14bytes  */

/*
* These are the definitions for the Line Control Register
*/
#define LCR_WLEN5  0x00	  /* Wordlength: 5 bits */
#define LCR_WLEN6  0x01	  /* Wordlength: 6 bits */
#define LCR_WLEN7  0x02	  /* Wordlength: 7 bits */
#define LCR_WLEN8  0x03	  /* Wordlength: 8 bits */
#define LCR_STOP 0x04 /* specify the number of generated stop bits '0'=1stop bits '1'=1.5bits when 5bit character length selected and 2bits otherwise */
#define LCR_PE  0x08 /*parity enable */
#define LCR_EPS 0x10 /*even parity select */
#define LCR_SPB 0x20 /*stick parity bit */
#define LCR_BCB 0x40 /* break control bit */
#define LCR_DLAB 0x80 /*divisor latch access bit */

/*
* These are the definitions for the Line Status Register
*/
#define LSR_DR 0x01 /*data ready indicator */
#define LSR_OE 0x02 /*overrun error indicator */
#define LSR_PE 0x04 /*parity error indicator */
#define LSR_FE 0x08 /*framing error indicator */
#define LSR_BI 0x10 /*break interrupt indicator */
#define LSR_TXRDY       0x20 /* Transmitter ready */
#define LSR_TXEMP       0x40 /* Transmitter empty */
#define LSR_FIFO_E       0x80 /*at least one error */

struct dtk_irda_cb {
	
	struct net_device *netdev;     /* Yes! we are some kind of netdevice */
	struct net_device_stats stats;
	
	struct irlap_cb *irlap;    /* The link layer we are binded to */
	struct qos_info qos;       /* QoS capabilities for this device */
	
	chipio_t io;               /* IrDA controller information */
	iobuff_t tx_buff;          /* Transmit buffer */
	iobuff_t rx_buff;          /* Receive buffer */
	
	__u8 ier;                  /* Interrupt enable register */
	__u32 new_speed;
	
	
};
int  dtk_irda_init(struct net_device* dev);

int  dtk_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev);
int dtk_irda_close();
#endif /* DTK_IRDA_H */