8bit-alu.vhd

来自「this is an 8 bit alu. to perform various」· VHDL 代码 · 共 55 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ALU_8bit is
  port(
       s : in std_logic_vector(2 downto 0);
       a : in std_logic_vector(8 downto 1);
       b : in std_logic_vector(8 downto 1);
       cin : in std_logic;
       op : inout std_logic_vector(8 downto 1);
       cout,V,AC : inout std_logic
       );
     end ;
       
architecture ALU_8bit of ALU_8bit is 

 component alumfa1
      port(s2,s1,s0,a1,b1:in std_logic;
       x1,y1:out std_logic);
     end component;
     
 component fadder_alu
     port(
        a : in std_logic_vector(7 downto 0);
        b : in std_logic_vector(7 downto 0);
        cin : in std_logic;
        sel : in std_logic;
        s : out std_logic_vector(7 downto 0);
        cout,OV,AC : out std_logic
     ) ;
   end component;
  
  signal im1,im2:std_logic_vector(8 downto 1);
  signal snot :std_logic;   
  
   begin
    snot <= (not s(2)); 
    k:for i in 1 to 8 generate
         l1: alumfa1 port map (s(2),s(1),s(0),a(i),b(i),im1(i),im2(i));
       end generate;
    l2: fadder_alu port map (im1(8 downto 1),im2(8 downto 1),cin,snot,op(8 downto 1),cout,V,AC);
    end ALU_8bit;
    configuration ALU_8bit_con of ALU_8bit is
  for ALU_8bit
  FOR K(1 TO 8)
  for l1:alumfa1 use entity work.alumfa1(alumfa1);
	END FOR;
			      end for;
    for l2:fadder_alu use entity work.fadder_alu(fadd);
      end for;
  end for;
end ALU_8bit_con;