m500auc.c

一个rc531代码

   start_timeout(42000); 	// count down with a period of 50 us
   			        // 42000 * 50 us = 2.1 s

  // wait until reset command recognized
   while (((ReadRawIO(RegCommand) & 0x3F) != 0x3F) && !T2IR);
   // while reset sequence in progress
   while ((ReadRawIO(RegCommand) & 0x3F) && !T2IR); 
   
   stop_timeout();  		// stop timeout counter

   if (T2IR) 		// If reader timeout occurs
   {
      status = MI_RESETERR; // respose of reader IC is not correct
      T2IR   = 0;
   }
   else
   {
      WriteRawIO(RegPage,0x80); // Dummy access in order to determine the bus 
                                // configuration
      // necessary read access 
      // after first write access, the returned value
      // should be zero ==> interface recognized
      if (ReadRawIO(RegCommand) != 0x00)
      {                           
          status = MI_INTERFACEERR;
      }
      WriteRawIO(RegPage,0x00); // configure to linear address mode
      	
   }
   return status;
}

///////////////////////////////////////////////////////////////////////
//      M I F A R E   M O D U L E   C O N F I G U R A T I O N
///////////////////////////////////////////////////////////////////////
char M500PcdConfig(void)
{
   char idata status;
   char idata i;
   char idata j;

   if ((status = M500PcdReset()) == MI_OK)
   {
     // test clock Q calibration - value in the range of 0x46 expected
     WriteIO(RegClockQControl,0x0);
     WriteIO(RegClockQControl,0x40);
     delay_50us(2);  // wait approximately 100 us - calibration in progress
     ClearBitMask(RegClockQControl,0x40); // clear bit ClkQCalib for 
                                          // further calibration

     // The following values for RegBitPhase and
     // RegRxThreshold represents an optimal
     // value for our demo package. For user
     // implementation some changes could be
     // necessary
     // initialize bit phase
     WriteIO(RegBitPhase,0xAD);      

     // initialize minlevel
     WriteIO(RegRxThreshold,0x9d);   
  
     // initialize receiver wait timing
     WriteIO(RegRxWait,0x06);   

     // disable auto power down
     WriteIO(RegRxControl2,0x01);

     // Depending on the processing speed of the
     // operation environment, the waterlevel 
     // can be adapted. (not very critical for
     // mifare applications)
     // initialize waterlevel to value 4
     WriteIO(RegFIFOLevel,0x04);   
     
     //Timer configuration
     WriteIO(RegTimerControl,0x06);  // TStopRxEnd=0,TStopRxBeg=1,
                                     // TStartTxEnd=1,TStartTxBeg=0  
                                     // timer must be stopped manually
     M500PcdSetTmo(106);             // short timeout

     WriteIO(RegIRqPinConfig,0x03); // interrupt active low enable

     M500PcdRfReset(1);            // Rf - reset and enable output driver   

     // initialize internal key memory     
     for (i = 0; i < 16; i++)
        for (j = 0; j < 12; j++)
           MKeys[i][j] = 0x00;
   }
   return status;
}

///////////////////////////////////////////////////////////////////////
//          M I F A R E   R E M O T E   A N T E N N A
//  Configuration of slave module
///////////////////////////////////////////////////////////////////////
char M500PcdMfInOutSlaveConfig(void)
{
   char idata status = MI_OK;

   FlushFIFO();    // empty FIFO
   ResetInfo(MInfo);   
   MSndBuffer[0] = 0x10; // addr low byte
   MSndBuffer[1] = 0x00; // addr high byte

   MSndBuffer[2] = 0x00; // Page
   MSndBuffer[3] = 0x7B; // RegTxControl modsource 11,InvTx2,Tx2RFEn,TX1RFEn
   MSndBuffer[4] = 0x3F; // RegCwConductance
   MSndBuffer[5] = 0x3F; // RFU13
   MSndBuffer[6] = 0x19; // RFU14
   MSndBuffer[7] = 0x13; // RegModWidth     
   MSndBuffer[8] = 0x00; // RFU16
   MSndBuffer[9] = 0x00; // RFU17
 
   MSndBuffer[10] = 0x00; // Page
   MSndBuffer[11] = 0x73; // RegRxControl1 
   MSndBuffer[12] = 0x08; // RegDecoderControl
   MSndBuffer[13] = 0x6c; // RegBitPhase     
   MSndBuffer[14] = 0xFF; // RegRxThreshold  
   MSndBuffer[15] = 0x00; // RFU1D
   MSndBuffer[16] = 0x00; // RegRxControl2   
   MSndBuffer[17] = 0x00; // RegClockQControl

   MSndBuffer[18] = 0x00; // Page
   MSndBuffer[19] = 0x06; // RegRxWait
   MSndBuffer[20] = 0x03; // RegChannelRedundancy
   MSndBuffer[21] = 0x63; // RegCRCPresetLSB    
   MSndBuffer[22] = 0x63; // RegCRCPresetMSB    
   MSndBuffer[23] = 0x0;  // RFU25
   MSndBuffer[24] = 0x04; // RegMfOutSelect enable mfout = manchester HT
   MSndBuffer[25] = 0x00; // RFU27
     
   // PAGE 5      FIFO, Timer and IRQ-Pin Configuration
   MSndBuffer[26] = 0x00; // Page
   MSndBuffer[27] = 0x08; // RegFIFOLevel       
   MSndBuffer[28] = 0x07; // RegTimerClock      
   MSndBuffer[29] = 0x06; // RegTimerControl    
   MSndBuffer[30] = 0x0A; // RegTimerReload     
   MSndBuffer[31] = 0x02; // RegIRqPinConfig    
   MSndBuffer[32] = 0x00; // RFU    
   MSndBuffer[33] = 0x00; // RFU
   MInfo.nBytesToSend   = 34;
         
   status = M500PcdCmd(PCD_WRITEE2,
                       MSndBuffer,
                       MRcvBuffer,
                       &MInfo); // write e2
   return status;
}

///////////////////////////////////////////////////////////////////////
//          M I F A R E   R E M O T E   A N T E N N A
//  Configuration of master module
///////////////////////////////////////////////////////////////////////
char M500PcdMfInOutMasterConfig(void)
{
   WriteIO(RegRxControl2,0x42);
   WriteIO(RegTxControl,0x10);
   WriteIO(RegBitPhase,0x11);

   return MI_OK;
}     

///////////////////////////////////////////////////////////////////////
//          M A S T E R   K E Y   L O A D 
///////////////////////////////////////////////////////////////////////
char M500PcdLoadMk(unsigned char  auth_mode,  // KEYA or KEYB
                   unsigned char  key_addr,   // 0 <= key_addr <= 15
                   unsigned char  *mk)        // 6 bytes uncoded master key
{
   unsigned char idata offset = (auth_mode == PICC_AUTHENT1A) ? 0 : 6;

   memcpy(MKeys[key_addr] + offset,mk,6);
   return MI_OK;
}
                  
///////////////////////////////////////////////////////////////////////
//          E E P R O M   M A S T E R   K E Y   L O A D 
///////////////////////////////////////////////////////////////////////
char M500PcdLoadKeyE2(unsigned char key_type,
                          unsigned char sector,
                          unsigned char *uncoded_keys)
{
   char idata status = MI_OK;
   // eeprom address calculation
   // 0x80 ... offset
   // key_sector ... sector
   // 0x18 ... 2 * 12 = 24 = 0x18
   unsigned short idata e2addr = 0x80 + sector * 0x18;
   unsigned char idata *e2addrbuf = (unsigned char*)&e2addr;
   unsigned char idata keycoded[12];

   if (key_type == PICC_AUTHENT1B)
      e2addr += 12; // key B offset   
   
   FlushFIFO();    // empty FIFO
   ResetInfo(MInfo);

   M500HostCodeKey(uncoded_keys,keycoded);
   memcpy(MSndBuffer,e2addrbuf,2); // write low and high byte of address
   MSndBuffer[2] = MSndBuffer[0];          // Move the LSB of the 2-bytes
   MSndBuffer[0] = MSndBuffer[1];  // address to the first byte
   MSndBuffer[1] = MSndBuffer[2];
   memcpy(&MSndBuffer[2],keycoded,12); // write 12 bytes of coded keys
   MInfo.nBytesToSend   = 14;
   
   // write load command
   status = M500PcdCmd(PCD_WRITEE2,
			MSndBuffer,
			MRcvBuffer,
			&MInfo);         
   
   return status;
}

///////////////////////////////////////////////////////////////////////
//          C O N F I G   I S O 1 4 4 4 3   T Y P E 
///////////////////////////////////////////////////////////////////////
char M500PcdConfigISOType(unsigned char type)
{
   if(type==TYPEA)
   {
     WriteIO(RegTxControl,0x5b); 	// Force100ASK, TX1 & TX2 enable
     WriteIO(RegCoderControl,0x19);     // Miller coding, 106kbps
     WriteIO(RegRxControl1,0x73);
     WriteIO(RegDecoderControl,0x08);   // Manchester Coding
     WriteIO(RegCRCPresetLSB,0x63);     // set CRC preset to 0x6363
     WriteIO(RegCRCPresetMSB,0x63);
     WriteIO(RegRxThreshold,0x88);  	// set max MinLevel & ColLevel.
     TYPE = TYPEA;	
   }
   else
   {
     WriteIO(RegTxControl,0x4b);      	// disable Force100ASk
     WriteIO(RegCoderControl,0x20);     // NRZ-L, TypeB baud 106kbps
     WriteIO(RegRxControl1,0x73);       //
     WriteIO(RegDecoderControl,0x19);   // BPSK coding
     WriteIO(RegCRCPresetLSB,0xff);     // set CRC preset to 0xffff
     WriteIO(RegCRCPresetMSB,0xff);
     WriteIO(RegTypeBFraming,0x23);     // EGT=0
     WriteIO(RegBPSKDemControl,0x3e);   // ignore EOF, on amp. detect
     WriteIO(RegModConductance,0x06);	// set modulation index at 12%
     WriteIO(RegRxThreshold,0x44);  // Reduce MinLevel & ColLevel.
				    // Increase higher nibble if carrier
				    // present but not detect
     TYPE = TYPEB;
   }
   return MI_OK;
}
     
///////////////////////////////////////////////////////////////////////
//          C O N F I G   M F O U T   S E L E C T 
///////////////////////////////////////////////////////////////////////
char M500PcdMfOutSelect(unsigned char type)
{
   WriteIO(RegMfOutSelect,type&0x07);
   return MI_OK;
}

///////////////////////////////////////////////////////////////////////
//          W R I T E   R E G I S T E R 
///////////////////////////////////////////////////////////////////////
char M500PcdWriteRegister(unsigned char Reg, unsigned char value)
{
   WriteIO(Reg,value);
   return MI_OK;
}

///////////////////////////////////////////////////////////////////////
//          R E A D   R E G I S T E R 
///////////////////////////////////////////////////////////////////////
char M500PcdReadRegister(unsigned char Reg)
{
   char value;
	
   value = ReadIO(Reg);
   return (value);
}

///////////////////////////////////////////////////////////////////////
//          M I F A R E    R E Q U E S T 
///////////////////////////////////////////////////////////////////////
char M500PiccRequest(unsigned char req_code, // request code ALL = 0x52 
                                             // or IDLE = 0x26 
                   unsigned char *atq)     // answer to request
{
   return M500PiccCommonRequest(req_code,atq);
}

///////////////////////////////////////////////////////////////////////
//          M I F A R E   C O M M O N   R E Q U E S T 
///////////////////////////////////////////////////////////////////////
char M500PiccCommonRequest(unsigned char req_code, 
                         unsigned char *atq)
{
   char idata status = MI_OK;

    //************* initialize ******************************
   WriteIO(RegChannelRedundancy,0x03); // RxCRC and TxCRC disable, parity enable
   ClearBitMask(RegControl,0x08);    // disable crypto 1 unit   
   WriteIO(RegBitFraming,0x07);        // set TxLastBits to 7 
   SetBitMask(RegTxControl,0x03);    // Tx2RF-En, Tx1RF-En enable
  
   M500PcdSetTmo(106);
 
   ResetInfo(MInfo);   
   MSndBuffer[0] = req_code;
   MInfo.nBytesToSend   = 1;   
   status = M500PcdCmd(PCD_TRANSCEIVE,
                      MSndBuffer,
                      MRcvBuffer,
                      &MInfo);
  
   if (status)      // error occured
   {
      *atq = 0;
   } 
   else 
   {
      if (MInfo.nBitsReceived != 16) // 2 bytes expected
      {
         *atq = 0;
         status = MI_BITCOUNTERR;
      } 
      else 
      {
         status = MI_OK;
         memcpy(atq,MRcvBuffer,2);
      }
   }
   return status; 
}

///////////////////////////////////////////////////////////////////////
//       M I F A R E   P I C C   A C T I V A T I O N    S E Q E N C E
///////////////////////////////////////////////////////////////////////
char M500PiccActivateIdle(unsigned char br,
                          unsigned char *atq, 
                          unsigned char *sak, 
                          unsigned char *uid, 
                          unsigned char *uid_len)
{
  unsigned char cascade_level;
  unsigned char sel_code;
  unsigned char uid_index;
  signed char status;