📄 m500auc.c
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WriteRawIO(RegInterruptRq,0x01); // reset IRQ bit
}
//************* TxIRQ Handling **************
if (irqBits & 0x10) // TxIRQ
{
WriteRawIO(RegInterruptRq,0x10); // reset IRQ bit
WriteRawIO(RegInterruptEn,0x82); // enable HiAlert Irq for
// response
if (MpIsrInfo->cmd == PICC_ANTICOLL1) // if cmd is anticollision
{ // switch off parity generation
WriteRawIO(RegChannelRedundancy,0x02); // RXCRC and TXCRC disable, parity disable
}
}
//************* HiAlertIRQ or RxIRQ Handling ******************
if (irqBits & 0x0E) // HiAlert, Idle or RxIRQ
{
// read some bytes (length of FIFO queue)
// into the receive buffer
nbytes = ReadRawIO(RegFIFOLength);
// read data from the FIFO and store them in the receive buffer
for (cnt=0; cnt<nbytes; cnt++)
{
MpIsrIn[MpIsrInfo->nBytesReceived] = ReadRawIO(RegFIFOData);
MpIsrInfo->nBytesReceived++;
}
WriteRawIO(RegInterruptRq,0x0A&irqBits);
// reset IRQ bit - idle irq will
// be deleted in a seperate section
}
//************** IdleIRQ Handling ***********
if (irqBits & 0x04) // Idle IRQ
{
WriteRawIO(RegInterruptEn,0x20); // disable Timer IRQ
WriteRawIO(RegInterruptRq,0x20); // disable Timer IRQ request
irqBits &= ~0x20; // clear Timer IRQ in local var
MpIsrInfo->irqSource &= ~0x20; // clear Timer IRQ in info var
// when idle received, then cancel
// timeout
WriteRawIO(RegInterruptRq,0x04); // reset IRQ bit
// status should still be MI_OK
// no error - only used for wake up
}
//************* TimerIRQ Handling ***********
if (irqBits & 0x20) // timer IRQ
{
WriteRawIO(RegInterruptRq,0x20); // reset IRQ bit
MpIsrInfo->status = MI_NOTAGERR; // timeout error
// otherwise ignore the interrupt
}
}
}
}
///////////////////////////////////////////////////////////////////////
// S e t T i m e o u t L E N G T H
///////////////////////////////////////////////////////////////////////
void M500PcdSetTmo(unsigned char tmoLength)
{
switch(tmoLength)
{ // timer clock frequency 13,56 MHz
case 0: // (0.302 ms) FWI=0
WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
WriteIO(RegTimerReload,0x21);// TReloadVal = 'h21 =33(dec)
break;
case 1: // (0.604 ms) FWI=1
WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
WriteIO(RegTimerReload,0x41);// TReloadVal = 'h41 =65(dec)
break;
case 2: // (1.208 ms) FWI=2
WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
WriteIO(RegTimerReload,0x81);// TReloadVal = 'h81 =129(dec)
break;
case 3: // (2.416 ms) FWI=3
WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
WriteIO(RegTimerReload,0x41);// TReloadVal = 'h41 =65(dec)
break;
case 4: // (4.833 ms) FWI=4
WriteIO(RegTimerClock,0x09); // TAutoRestart=0,TPrescale=4*128
WriteIO(RegTimerReload,0x81);// TReloadVal = 'h81 =129(dec)
break;
case 5: // (9.666 ms) FWI=5
WriteIO(RegTimerClock,0x0B); // TAutoRestart=0,TPrescale=16*128
WriteIO(RegTimerReload,0x41);// TReloadVal = 'h41 =65(dec)
break;
case 6: // (19.33 ms) FWI=6
WriteIO(RegTimerClock,0x0B); // TAutoRestart=0,TPrescale=16*128
WriteIO(RegTimerReload,0x81);// TReloadVal = 'h81 =129(dec)
break;
case 7: // (38.66 ms) FWI=7
WriteIO(RegTimerClock,0x0D); // TAutoRestart=0,TPrescale=64*128
WriteIO(RegTimerReload,0x41);// TReloadVal = 'h41 =65(dec)
break;
case 8: // (77.32 ms) FWI=8
WriteIO(RegTimerClock,0x0D); // TAutoRestart=0,TPrescale=64*128
WriteIO(RegTimerReload,0x81);// TReloadVal = 'h81 =129(dec)
break;
case 9: // (154.6 ms) FWI=9
WriteIO(RegTimerClock,0x0F); // TAutoRestart=0,TPrescale=256*128
WriteIO(RegTimerReload,0x41);// TReloadVal = 'h41 =65(dec)
break;
case 10: // (309.3 ms) FWI=10
WriteIO(RegTimerClock,0x0F); // TAutoRestart=0,TPrescale=256*128
WriteIO(RegTimerReload,0x81);// TReloadVal = 'h81 =129(dec)
break;
case 11: // (618.6 ms) FWI=11
WriteIO(RegTimerClock,0x13); // TAutoRestart=0,TPrescale=4096*128
WriteIO(RegTimerReload,0x11);// TReloadVal = 'h21 =17(dec)
break;
case 12: // (1.2371 s) FWI=12
WriteIO(RegTimerClock,0x13); // TAutoRestart=0,TPrescale=4096*128
WriteIO(RegTimerReload,0x21);// TReloadVal = 'h41 =33(dec)
break;
case 13: // (2.4742 s) FWI=13
WriteIO(RegTimerClock,0x13); // TAutoRestart=0,TPrescale=4096*128
WriteIO(RegTimerReload,0x41);// TReloadVal = 'h81 =65(dec)
break;
case 14: // (4.9485 s) FWI=14
WriteIO(RegTimerClock,0x13); // TAutoRestart=0,TPrescale=4096*128
WriteIO(RegTimerReload,0x81);// TReloadVal = 'h81 =129(dec)
break;
default: //
WriteIO(RegTimerClock,0x07); // TAutoRestart=0,TPrescale=128
WriteIO(RegTimerReload,tmoLength);// TReloadVal = 'h6a =tmoLength(dec)
break;
}
}
//////////////////////////////////////////////////////////////////////
// W R I T E A P C D C O M M A N D
///////////////////////////////////////////////////////////////////////
char M500PcdCmd(unsigned char cmd,
volatile unsigned char* send,
volatile unsigned char* rcv,
volatile MfCmdInfo *info)
{
char idata status = MI_OK;
char idata tmpStatus ;
unsigned char idata lastBits;
unsigned char idata irqEn = 0x00;
unsigned char idata waitFor = 0x00;
unsigned char idata timerCtl = 0x00;
WriteIO(RegInterruptEn,0x7F); // disable all interrupts
WriteIO(RegInterruptRq,0x7F); // reset interrupt requests
WriteIO(RegCommand,PCD_IDLE); // terminate probably running command
FlushFIFO(); // flush FIFO buffer
// save info structures to module pointers
MpIsrInfo = info;
MpIsrOut = send;
MpIsrIn = rcv;
info->irqSource = 0x0; // reset interrupt flags
// depending on the command code, appropriate interrupts are enabled (irqEn)
// and the commit interrupt is choosen (waitFor).
switch(cmd)
{
case PCD_IDLE: // nothing else required
irqEn = 0x00;
waitFor = 0x00;
break;
case PCD_WRITEE2: // LoAlert and TxIRq
irqEn = 0x11;
waitFor = 0x10;
break;
case PCD_READE2: // HiAlert, LoAlert and IdleIRq
irqEn = 0x07;
waitFor = 0x04;
break;
case PCD_LOADCONFIG: // IdleIRq
case PCD_LOADKEYE2: // IdleIRq
case PCD_AUTHENT1: // IdleIRq
irqEn = 0x05;
waitFor = 0x04;
break;
case PCD_CALCCRC: // LoAlert and TxIRq
irqEn = 0x11;
waitFor = 0x10;
break;
case PCD_AUTHENT2: // IdleIRq
irqEn = 0x04;
waitFor = 0x04;
break;
case PCD_RECEIVE: // HiAlert and IdleIRq
info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
irqEn = 0x06;
waitFor = 0x04;
break;
case PCD_LOADKEY: // IdleIRq
irqEn = 0x05;
waitFor = 0x04;
break;
case PCD_TRANSMIT: // LoAlert and IdleIRq
irqEn = 0x05;
waitFor = 0x04;
break;
case PCD_TRANSCEIVE: // TxIrq, RxIrq, IdleIRq and LoAlert
info->nBitsReceived = -(ReadIO(RegBitFraming) >> 4);
irqEn = 0x3D;
waitFor = 0x04;
break;
default:
status = MI_UNKNOWN_COMMAND;
}
if (status == MI_OK)
{
// Initialize uC Timer for global Timeout management
irqEn |= 0x20; // always enable timout irq
waitFor |= 0x20; // always wait for timeout
start_timeout(4000); // initialise and start guard timer for reader
// 50us resolution, 200ms
WriteIO(RegInterruptEn,irqEn | 0x80); //necessary interrupts are enabled
WriteIO(RegCommand,cmd); //start command
// wait for commmand completion
// a command is completed, if the corresponding interrupt occurs
// or a timeout is signaled
while (!(MpIsrInfo->irqSource & waitFor
|| T2IR)); // wait for cmd completion or timeout
WriteIO(RegInterruptEn,0x7F); // disable all interrupts
WriteIO(RegInterruptRq,0x7F); // clear all interrupt requests
SetBitMask(RegControl,0x04); // stop timer now
stop_timeout(); // stop timeout for reader
WriteIO(RegCommand,PCD_IDLE); // reset command register
if (!(MpIsrInfo->irqSource & waitFor)) // reader has not terminated
{ // timer 2 expired
status = MI_ACCESSTIMEOUT;
}
else
status = MpIsrInfo->status; // set status
if (status == MI_OK) // no timeout error occured
{
if (tmpStatus = (ReadIO(RegErrorFlag) & 0x17)) // error occured
{
if (tmpStatus & 0x01) // collision detected
{
info->collPos = ReadIO(RegCollpos); // read collision position
status = MI_COLLERR;
}
else
{
info->collPos = 0;
if (tmpStatus & 0x02) // parity error
{
status = MI_PARITYERR;
}
}
if (tmpStatus & 0x04) // framing error
{
status = MI_FRAMINGERR;
}
if (tmpStatus & 0x10) // FIFO overflow
{
FlushFIFO();
status = MI_OVFLERR;
}
if (tmpStatus & 0x08) //CRC error
{
status = MI_CRCERR;
}
if (status == MI_OK)
status = MI_NY_IMPLEMENTED;
// key error occures always, because of
// missing crypto 1 keys loaded
}
// if the last command was TRANSCEIVE, the number of
// received bits must be calculated - even if an error occured
if (cmd == PCD_TRANSCEIVE)
{
// number of bits in the last byte
lastBits = ReadIO(RegSecondaryStatus) & 0x07;
if (lastBits)
info->nBitsReceived += (info->nBytesReceived-1) * 8 + lastBits;
else
info->nBitsReceived += info->nBytesReceived * 8;
}
}
else
{
info->collPos = 0x00;
}
}
MpIsrInfo = 0; // reset interface variables for ISR
MpIsrOut = 0;
MpIsrIn = 0;
return status;
}
//////////////////////////////////////////////////////////////////////
// S E T A B I T M A S K
///////////////////////////////////////////////////////////////////////
char SetBitMask(unsigned char reg,unsigned char mask) //
{
char idata tmp = 0x0;
tmp = ReadIO(reg);
WriteIO(reg,tmp | mask); // set bit mask
return 0x0;
}
//////////////////////////////////////////////////////////////////////
// C L E A R A B I T M A S K
///////////////////////////////////////////////////////////////////////
char ClearBitMask(unsigned char reg,unsigned char mask) //
{
char idata tmp = 0x0;
tmp = ReadIO(reg);
WriteIO(reg,tmp & ~mask); // clear bit mask
return 0x0;
}
///////////////////////////////////////////////////////////////////////
// F L U S H F I F O
///////////////////////////////////////////////////////////////////////
void FlushFIFO(void)
{
SetBitMask(RegControl,0x01);
}
///////////////////////////////////////////////////////////////////////
// M I F A R E M O D U L E R E S E T
///////////////////////////////////////////////////////////////////////
char M500PcdReset(void)
{
char idata status = MI_OK;
RC500RST = 0; // clear reset pin
delay_50us(500); // wait for 25ms
RC500RST = 1; // reset RC500
delay_50us(50); // wait for 2.5ms
RC500RST = 0; // clear reset pin
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