compile_all.v

来自「IC内核的设计源码！其中包含MP3内核」· Verilog 代码 · 共 10 行

`include "command.v"
`include "sdr_sdram.v"
`include "control_interface.v"
`include "sdr_sdram_tb.v"
`include "mt48lc8m16a2.v"
`include "sdr_data_path.v"
`include "pll1.v"
`include "altclklock.v"