_primary.vhd

来自「IC内核的设计源码！其中包含MP3内核」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity pll1 is
    port(
        inclock         : in     vl_logic;
        locked          : out    vl_logic;
        clock0          : out    vl_logic;
        clock1          : out    vl_logic
    );
end pll1;