_info

IC内核的设计源码！其中包含MP3内核

m255
o
dD:\Projects\altera\lpcores\sdr\release\V1_1\simulation
valtclklock
IcNeKkSXZi8CezdBb<:3S>1
V9[;?M8o6KGRDP5`?6=E[z1
dG:\HDL_DOC\IP\sdram\simulation
w960774310
FG:/HDL_DOC/IP/sdram/source/altclklock.v
L0 37
OE;L;5.5b;17
r1
31
o-work work
vcommand
IgUd0e`de]U:>4eW3m2fK70
dD:\Projects\altera\lpcores\sdr\release\V1_2\simulation
w963398607
FD:/Projects/altera/lpcores/sdr/release/V1_2/simulation/Command.v
Fparams.v
OP;L;5.3d;15
V9P;4Yl3]nOQ_XLY<Q;@Hn1
31
o-work work
vcontrol_interface
InJ?zR@:?Ic0LE6SDDcTLH0
w958500438
Fcontrol_interface.v
Fparams.v
OP;L;5.3d;15
VKiZlacfBig]=O8DBB0^eN2
31
o-work work
vmt48lc8m16a2
IigQLGln6ESdL;zNj4EFim3
VDhgbnL2?dRIbTQjh0Zc_Z2
dG:\HDL_DOC\IP\sdram\simulation
w959012174
FG:/HDL_DOC/IP/sdram/model/mt48lc8m16a2.v
L0 44
OE;L;5.5b;17
r1
31
o-work work
vpll1
IzQ5WBKzb9lRo<2n1bjV;M2
V@CH?[_eACOd?oN=?KAoSa3
dG:\HDL_DOC\IP\sdram\simulation
w959012064
FG:/HDL_DOC/IP/sdram/source/PLL1.v
L0 37
OE;L;5.5b;17
r1
31
o-work work
vsdr_data_path
Ii@U^M8jLm]C7ZmciBCkZa3
w959062651
Fsdr_data_path.v
Fparams.v
OP;L;5.3d;15
V;P;9iL]HLjDQhdL<M47G:1
31
o-work work
vsdr_sdram
IeY5>G^LjBQ:iWoIEK>>;c3
w959065987
Fsdr_sdram.v
Fparams.v
OP;L;5.3d;15
VjoXz=544Rk`M<;o5R>Q5[3
31
o-work work
vsdr_sdram_tb
IGD4>co=zH1o]4KM2C>EFl1
dD:\Projects\altera\lpcores\sdr\release\V1_2\simulation
w963443271
FD:/Projects/altera/lpcores/sdr/release/V1_2/simulation/sdr_sdram_tb.v
Fparams.v
OP;L;5.3d;15
VB4NAZHh=L:g5<EG[fZA6T0
31
o-work work