_primary.vhd

来自「IC内核的设计源码！其中包含MP3内核」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity sdr_data_path is
    port(
        clk             : in     vl_logic;
        reset_n         : in     vl_logic;
        oe              : in     vl_logic;
        datain          : in     vl_logic_vector(31 downto 0);
        dm              : in     vl_logic_vector(3 downto 0);
        dataout         : out    vl_logic_vector(31 downto 0);
        dqin            : in     vl_logic_vector(31 downto 0);
        dqout           : out    vl_logic_vector(31 downto 0);
        dqm             : out    vl_logic_vector(3 downto 0)
    );
end sdr_data_path;