sdr_sdram.sxr

IC内核的设计源码！其中包含MP3内核

Inst: BA[1] BA_1_
Inst: rw_shift[0] rw_shift_0_
Inst: rw_shift[1] rw_shift_1_
Inst: rp_shift[3] rp_shift_3_
Inst: SA_12_i[1] SA_12_i_1_
Inst: G_134 G_134
Inst: SA_12_i[4] SA_12_i_4_
Inst: SA_12_i[5] SA_12_i_5_
Inst: SA_12_i[8] SA_12_i_8_
Inst: command_delay_7_i_and2[6] command_delay_7_i_and2_6_
Inst: command_delay_7_i_and2[5] command_delay_7_i_and2_5_
Inst: command_delay_7_i_and2[4] command_delay_7_i_and2_4_
Inst: command_delay_7_i_and2[3] command_delay_7_i_and2_3_
Inst: command_delay_7_i_and2[2] command_delay_7_i_and2_2_
Inst: command_delay_7_i_and2[1] command_delay_7_i_and2_1_
Inst: command_delay_7_i_and2[0] command_delay_7_i_and2_0_
Inst: command_done_6_i_and2 command_done_6_i_and2
Inst: rp_done11_0_and2 rp_done11_0_and2
Inst: G_136 G_136
Inst: WE_N_13_0_iv_0 WE_N_13_0_iv_0
Inst: CS_N_9_2_0_0[0] CS_N_9_2_0_0_0_
Inst: rp_shift_7_0[2] rp_shift_7_0_2_
Inst: rp_shift_7_0[1] rp_shift_7_0_1_
Inst: rp_shift_7_0[0] rp_shift_7_0_0_
Inst: rp_done_6_0 rp_done_6_0
Inst: G_131 G_131
Inst: BA_8_0_and2[1] BA_8_0_and2_1_
Inst: CM_ACK13_0_and2 CM_ACK13_0_and2
Inst: G_161 G_161
Inst: CAS_N_13_i CAS_N_13_i
Inst: CM_ACK14_i CM_ACK14_i
Inst: do_rw_8_i_and2 do_rw_8_i_and2
Inst: SA_8_2_0_a1_i SA_8_2_0_a1_i
Inst: un1_do_rw21_7_i un1_do_rw21_7_i
Inst: un1_do_rw21_2_i un1_do_rw21_2_i
Inst: SA_12_i[2] SA_12_i_2_
Inst: SA_12_i[3] SA_12_i_3_
Inst: rw_shift_10_iv_0[0] rw_shift_10_iv_0_0_
Inst: rw_shift_10_iv_0_and2[0] rw_shift_10_iv_0_and2_0_
Inst: BA_8_0_and2[0] BA_8_0_and2_0_
Inst: SA_12_i[9] SA_12_i_9_
Inst: SA_12_i[11] SA_12_i_11_
Inst: un1_un1_un1_SC_PM_0 un1_un1_un1_SC_PM_0
Inst: un1_un1_un1_SC_PM_0_and2.G_164 un1_un1_un1_SC_PM_0_and2_G_164
Inst: G_107 G_107
Inst: oe4_10_iv_i_and2 oe4_10_iv_i_and2
Inst: G_105_L G_105_L
Inst: G_105 G_105
Inst: oe1_6_i_and2 oe1_6_i_and2
Inst: SA_12_i[7] SA_12_i_7_
Inst: SA_12_i[6] SA_12_i_6_
Inst: SA_12_i[0] SA_12_i_0_
Inst: un1_SC_PM_6_i_L un1_SC_PM_6_i_L
Inst: un1_SC_PM_6_i un1_SC_PM_6_i
Inst: un1_SC_PM_6_i_and2_0.G_173 un1_SC_PM_6_i_and2_0_G_173
Inst: un1_SC_PM_6_i_and2_L un1_SC_PM_6_i_and2_L
Inst: un1_SC_PM_6_i_and2 un1_SC_PM_6_i_and2
Inst: G_147 G_147
Inst: CS_N_9_0_and2[1] CS_N_9_0_and2_1_
Inst: do_writea110_0_and2 do_writea110_0_and2
Inst: do_reada13_0_and2 do_reada13_0_and2
Inst: RAS_N_13_0_and2 RAS_N_13_0_and2
Inst: do_precharge13_0_and2 do_precharge13_0_and2
Inst: do_load_mode13_0_and2 do_load_mode13_0_and2
Inst: RAS_N_13_0 RAS_N_13_0
Inst: G_157 G_157
Inst: N_229_i_L N_229_i_L
Inst: G_134_rep0 G_134_rep0
Inst: WE_N_13_0_iv_0_and2_0_cas WE_N_13_0_iv_0_and2_0_cas
Inst: WE_N_13_0_iv_0_and2_0_lut WE_N_13_0_iv_0_and2_0_lut
Inst: WE_N_13_0_iv_0_and2_0_cand WE_N_13_0_iv_0_and2_0_cand
Inst: WE_N_13_0_iv_0_and2_0 WE_N_13_0_iv_0_and2_0
Inst: G_104_cas G_104_cas
Inst: G_104_lut G_104_lut
Inst: G_104_cand G_104_cand
Inst: G_104 G_104
Inst: SA_12_i_cas[10] SA_12_i_cas_10_
Inst: SA_12_i_lut[10] SA_12_i_lut_10_
Inst: SA_12_i_cand[10] SA_12_i_cand_10_
Inst: do_refresh13_0_and2_cas do_refresh13_0_and2_cas
Inst: do_refresh13_0_and2_lut do_refresh13_0_and2_lut
Inst: do_refresh13_0_and2_cand do_refresh13_0_and2_cand
Net: LOAD_MODE LOAD_MODE
Net: PRECHARGE PRECHARGE
Net: RAS_N_13_0_and2 RAS_N_13_0_and2
Net: READA READA
Net: G_134_rep0 G_134_rep0
Net: REFRESH REFRESH
Net: WRITEA WRITEA
Net: G_147 G_147
Net: SC_BL[1] SC_BL_1_
Net: SC_BL[0] SC_BL_0_
Net: un1_un1_SC_BL_2 un1_un1_SC_BL_2
Net: SC_BL[3] SC_BL_3_
Net: SC_BL[2] SC_BL_2_
Net: G_173 G_173
Net: I_115 I_115
Net: un1_SC_PM_6_i_and2 un1_SC_PM_6_i_and2
Net: SADDR[0] SADDR_0_
Net: SADDR[9] SADDR_9_
Net: SADDR[6] SADDR_6_
Net: SADDR[15] SADDR_15_
Net: SADDR[7] SADDR_7_
Net: SADDR[16] SADDR_16_
Net: G_164 G_164
Net: SADDR[18] SADDR_18_
Net: SADDR[20] SADDR_20_
Net: SADDR[3] SADDR_3_
Net: SADDR[12] SADDR_12_
Net: SADDR[2] SADDR_2_
Net: SADDR[11] SADDR_11_
Net: SC_RC[1] SC_RC_1_
Net: SC_RC[0] SC_RC_0_
Net: SC_PM SC_PM
Net: SA_8_2_0_a1_i SA_8_2_0_a1_i
Net: SADDR[19] SADDR_19_
Net: G_161 G_161
Net: REF_REQ REF_REQ
Net: SADDR[21] SADDR_21_
Net: G_131 G_131
Net: SADDR[22] SADDR_22_
Net: WE_N_13_0_iv_0_and2_0 WE_N_13_0_iv_0_and2_0
Net: G_136 G_136
Net: G_136_lc G_136_lc
Net: SADDR[8] SADDR_8_
Net: SADDR[17] SADDR_17_
Net: SADDR[5] SADDR_5_
Net: SADDR[14] SADDR_14_
Net: SADDR[4] SADDR_4_
Net: SADDR[13] SADDR_13_
Net: G_134_lc G_134_lc
Net: G_134 G_134
Net: SADDR[1] SADDR_1_
Net: SADDR[10] SADDR_10_
Net: rp_shift_i[2] rp_shift_i_2_
Net: rp_shift_7_0[2] rp_shift_7_0_2_
Net: rp_shift_i[1] rp_shift_i_1_
Net: rp_shift_7_0[1] rp_shift_7_0_1_
Net: rp_shift_i[0] rp_shift_i_0_
Net: rp_shift_7_0[0] rp_shift_7_0_0_
Net: command_delay_i[7] command_delay_i_7_
Net: command_delay_i[6] command_delay_i_6_
Net: command_delay_7_i_and2[6] command_delay_7_i_and2_6_
Net: command_delay_i[5] command_delay_i_5_
Net: command_delay_7_i_and2[5] command_delay_7_i_and2_5_
Net: command_delay_i[4] command_delay_i_4_
Net: command_delay_7_i_and2[4] command_delay_7_i_and2_4_
Net: command_delay_i[3] command_delay_i_3_
Net: command_delay_7_i_and2[3] command_delay_7_i_and2_3_
Net: command_delay_i[2] command_delay_i_2_
Net: command_delay_7_i_and2[2] command_delay_7_i_and2_2_
Net: command_delay_i[1] command_delay_i_1_
Net: command_delay_7_i_and2[1] command_delay_7_i_and2_1_
Net: command_delay_i[0] command_delay_i_0_
Net: command_delay_7_i_and2[0] command_delay_7_i_and2_0_
Net: oe4_i oe4_i
Net: oe4_10_iv_i_and2 oe4_10_iv_i_and2
Net: un1_un1_un1_SC_PM_0 un1_un1_un1_SC_PM_0
Net: CM_ACK_i CM_ACK_i
Net: G_104 G_104
Net: CM_ACK13_0_and2 CM_ACK13_0_and2
Net: do_rw_i do_rw_i
Net: do_rw_8_i_and2 do_rw_8_i_and2
Net: un1_do_rw21_7_i un1_do_rw21_7_i
Net: command_done_i command_done_i
Net: command_done_6_i_and2 command_done_6_i_and2
Net: rp_done_i rp_done_i
Net: rp_done_6_0 rp_done_6_0
Net: CKE CKE
Net: do_load_mode do_load_mode
Net: do_load_mode13_0_and2 do_load_mode13_0_and2
Net: do_precharge do_precharge
Net: do_precharge13_0_and2 do_precharge13_0_and2
Net: do_writea1 do_writea1
Net: do_reada13_0_and2 do_reada13_0_and2
Net: do_writea do_writea
Net: do_writea110_0_and2 do_writea110_0_and2
Net: oe3 oe3
Net: oe2 oe2
Net: G_105 G_105
Net: do_refresh13_0_and2 do_refresh13_0_and2
Net: rw_flag rw_flag
Net: do_reada do_reada
Net: N_229_i N_229_i
Net: oe1 oe1
Net: oe1_6_i_and2 oe1_6_i_and2
Net: sc_pm_i sc_pm_i
Net: REF_ACK REF_ACK
Net: do_refresh do_refresh
Net: CM_ACK14_i CM_ACK14_i
Net: OE OE
Net: G_157 G_157
Net: G_107 G_107
Net: WE_N WE_N
Net: WE_N_13_0_iv_0 WE_N_13_0_iv_0
Net: CAS_N CAS_N
Net: CAS_N_13_i CAS_N_13_i
Net: RAS_N RAS_N
Net: RAS_N_13_0 RAS_N_13_0
Net: oe_shift[0] oe_shift_0_
Net: I_99 I_99
Net: oe_shift[1] oe_shift_1_
Net: I_105 I_105
Net: oe_shift[2] oe_shift_2_
Net: I_113 I_113
Net: oe_shift[3] oe_shift_3_
Net: I_121 I_121
Net: oe_shift[4] oe_shift_4_
Net: I_130 I_130
Net: oe_shift[5] oe_shift_5_
Net: I_139 I_139
Net: oe_shift[6] oe_shift_6_
Net: I_149 I_149
Net: un1_SC_PM_6_i un1_SC_PM_6_i
Net: SA[0] SA_0_
Net: SA_12_i[0] SA_12_i_0_
Net: SA[1] SA_1_
Net: SA_12_i[1] SA_12_i_1_
Net: SA[2] SA_2_
Net: SA_12_i[2] SA_12_i_2_
Net: SA[3] SA_3_
Net: SA_12_i[3] SA_12_i_3_
Net: SA[4] SA_4_
Net: SA_12_i[4] SA_12_i_4_
Net: SA[5] SA_5_
Net: SA_12_i[5] SA_12_i_5_
Net: SA[6] SA_6_
Net: SA_12_i[6] SA_12_i_6_
Net: SA[7] SA_7_
Net: SA_12_i[7] SA_12_i_7_
Net: SA[8] SA_8_
Net: SA_12_i[8] SA_12_i_8_
Net: SA[9] SA_9_
Net: SA_12_i[9] SA_12_i_9_
Net: SA[10] SA_10_
Net: SA_12_i[10] SA_12_i_10_
Net: SA[11] SA_11_
Net: SA_12_i[11] SA_12_i_11_
Net: CS_N[0] CS_N_0_
Net: CS_N_9_2_0_0[0] CS_N_9_2_0_0_0_
Net: CS_N[1] CS_N_1_
Net: CS_N_9_0_and2[1] CS_N_9_0_and2_1_
Net: BA[0] BA_0_
Net: BA_8_0_and2[0] BA_8_0_and2_0_
Net: BA[1] BA_1_
Net: BA_8_0_and2[1] BA_8_0_and2_1_
Net: rw_shift[0] rw_shift_0_
Net: rw_shift_10_iv_0[0] rw_shift_10_iv_0_0_
Net: rw_shift[1] rw_shift_1_
Net: rw_shift_10_iv_0_and2[0] rw_shift_10_iv_0_and2_0_
Net: un1_do_rw21_2_i un1_do_rw21_2_i
Net: rp_shift[3] rp_shift_3_
Net: rp_done11_0_and2 rp_done11_0_and2
Net: CLK CLK
Net: RESET_N RESET_N
Net: GND GND
Net: VCC VCC
Net: N_1 N_1
Net: G_105_L G_105_L
Net: un1_SC_PM_6_i_L un1_SC_PM_6_i_L
Net: un1_SC_PM_6_i_and2_L un1_SC_PM_6_i_and2_L
Net: N_2 N_2
Net: WE_N_13_0_iv_0_and2_0_lut WE_N_13_0_iv_0_and2_0_lut
Net: N_3 N_3
Net: N_4 N_4
Net: G_104_lut G_104_lut
Net: N_5 N_5
Net: N_6 N_6
Net: SA_12_i_lut[10] SA_12_i_lut_10_
Net: N_8 N_8
Net: do_refresh13_0_and2_lut do_refresh13_0_and2_lut
EndView command command
BeginView L4_FFF8 L4_FFF8
Inst: G_1 G_1
Inst: G_2 G_2
Inst: G_3 G_3
Net: I0 I0
Net: I1 I1
Net: I2 I2
Net: I3 I3
Net: N_2 N_2
Net: N_3 N_3
Net: Z Z
EndView L4_FFF8 L4_FFF8
BeginView L4_60 L4_60
Inst: G_1 G_1
Inst: G_2 G_2
Inst: G_3 G_3
Inst: G_4 G_4
Inst: G_5 G_5
Net: I0 I0
Net: I1 I1
Net: I2 I2
Net: I3 I3
Net: N_2 N_2
Net: N_3 N_3
Net: N_4 N_4
Net: N_5 N_5
Net: Z Z
EndView L4_60 L4_60
BeginView sdr_data_path sdr_data_path
Inst: DQOUT[0] DQOUT_0_
Inst: DQOUT[1] DQOUT_1_
Inst: DQOUT[2] DQOUT_2_
Inst: DQOUT[3] DQOUT_3_
Inst: DQOUT[4] DQOUT_4_
Inst: DQOUT[5] DQOUT_5_
Inst: DQOUT[6] DQOUT_6_
Inst: DQOUT[7] DQOUT_7_
Inst: DQOUT[8] DQOUT_8_
Inst: DQOUT[9] DQOUT_9_
Inst: DQOUT[10] DQOUT_10_
Inst: DQOUT[11] DQOUT_11_
Inst: DQOUT[12] DQOUT_12_
Inst: DQOUT[13] DQOUT_13_
Inst: DQOUT[14] DQOUT_14_
Inst: DQOUT[15] DQOUT_15_
Inst: DQOUT[16] DQOUT_16_
Inst: DQOUT[17] DQOUT_17_
Inst: DQOUT[18] DQOUT_18_
Inst: DQOUT[19] DQOUT_19_
Inst: DQOUT[20] DQOUT_20_
Inst: DQOUT[21] DQOUT_21_
Inst: DQOUT[22] DQOUT_22_
Inst: DQOUT[23] DQOUT_23_
Inst: DQOUT[24] DQOUT_24_
Inst: DQOUT[25] DQOUT_25_
Inst: DQOUT[26] DQOUT_26_
Inst: DQOUT[27] DQOUT_27_
Inst: DQOUT[28] DQOUT_28_
Inst: DQOUT[29] DQOUT_29_
Inst: DQOUT[30] DQOUT_30_
Inst: DQOUT[31] DQOUT_31_
Inst: DIN1[0] DIN1_0_
Inst: DIN1[1] DIN1_1_
Inst: DIN1[2] DIN1_2_
Inst: DIN1[3] DIN1_3_
Inst: DIN1[4] DIN1_4_
Inst: DIN1[5] DIN1_5_
Inst: DIN1[6] DIN1_6_
Inst: DIN1[7] DIN1_7_
Inst: DIN1[8] DIN1_8_
Inst: DIN1[9] DIN1_9_
Inst: DIN1[10] DIN1_10_
Inst: DIN1[11] DIN1_11_
Inst: DIN1[12] DIN1_12_
Inst: DIN1[13] DIN1_13_
Inst: DIN1[14] DIN1_14_
Inst: DIN1[15] DIN1_15_
Inst: DIN1[16] DIN1_16_
Inst: DIN1[17] DIN1_17_
Inst: DIN1[18] DIN1_18_
Inst: DIN1[19] DIN1_19_
Inst: DIN1[20] DIN1_20_
Inst: DIN1[21] DIN1_21_
Inst: DIN1[22] DIN1_22_
Inst: DIN1[23] DIN1_23_
Inst: DIN1[24] DIN1_24_
Inst: DIN1[25] DIN1_25_
Inst: DIN1[26] DIN1_26_
Inst: DIN1[27] DIN1_27_
Inst: DIN1[28] DIN1_28_
Inst: DIN1[29] DIN1_29_
Inst: DIN1[30] DIN1_30_
Inst: DIN1[31] DIN1_31_
Inst: DM1[0] DM1_0_
Inst: DM1[1] DM1_1_
Inst: DM1[2] DM1_2_
Inst: DM1[3] DM1_3_
Inst: DQM[0] DQM_0_
Inst: DQM[1] DQM_1_
Inst: DQM[2] DQM_2_
Inst: DQM[3] DQM_3_
Net: DQOUT[0] DQOUT_0_
Net: DQOUT[1] DQOUT_1_
Net: DQOUT[2] DQOUT_2_
Net: DQOUT[3] DQOUT_3_
Net: DQOUT[4] DQOUT_4_
Net: DQOUT[5] DQOUT_5_
Net: DQOUT[6] DQOUT_6_
Net: DQOUT[7] DQOUT_7_
Net: DQOUT[8] DQOUT_8_
Net: DQOUT[9] DQOUT_9_
Net: DQOUT[10] DQOUT_10_
Net: DQOUT[11] DQOUT_11_
Net: DQOUT[12] DQOUT_12_
Net: DQOUT[13] DQOUT_13_
Net: DQOUT[14] DQOUT_14_
Net: DQOUT[15] DQOUT_15_
Net: DQOUT[16] DQOUT_16_
Net: DQOUT[17] DQOUT_17_
Net: DQOUT[18] DQOUT_18_
Net: DQOUT[19] DQOUT_19_
Net: DQOUT[20] DQOUT_20_
Net: DQOUT[21] DQOUT_21_
Net: DQOUT[22] DQOUT_22_
Net: DQOUT[23] DQOUT_23_
Net: DQOUT[24] DQOUT_24_
Net: DQOUT[25] DQOUT_25_
Net: DQOUT[26] DQOUT_26_
Net: DQOUT[27] DQOUT_27_
Net: DQOUT[28] DQOUT_28_
Net: DQOUT[29] DQOUT_29_
Net: DQOUT[30] DQOUT_30_
Net: DQOUT[31] DQOUT_31_
Net: DIN1[0] DIN1_0_
Net: DATAIN[0] DATAIN_0_
Net: DIN1[1] DIN1_1_
Net: DATAIN[1] DATAIN_1_
Net: DIN1[2] DIN1_2_
Net: DATAIN[2] DATAIN_2_
Net: DIN1[3] DIN1_3_
Net: DATAIN[3] DATAIN_3_
Net: DIN1[4] DIN1_4_
Net: DATAIN[4] DATAIN_4_
Net: DIN1[5] DIN1_5_
Net: DATAIN[5] DATAIN_5_
Net: DIN1[6] DIN1_6_
Net: DATAIN[6] DATAIN_6_
Net: DIN1[7] DIN1_7_
Net: DATAIN[7] DATAIN_7_
Net: DIN1[8] DIN1_8_
Net: DATAIN[8] DATAIN_8_
Net: DIN1[9] DIN1_9_
Net: DATAIN[9] DATAIN_9_
Net: DIN1[10] DIN1_10_
Net: DATAIN[10] DATAIN_10_
Net: DIN1[11] DIN1_11_
Net: DATAIN[11] DATAIN_11_
Net: DIN1[12] DIN1_12_
Net: DATAIN[12] DATAIN_12_
Net: DIN1[13] DIN1_13_
Net: DATAIN[13] DATAIN_13_
Net: DIN1[14] DIN1_14_
Net: DATAIN[14] DATAIN_14_
Net: DIN1[15] DIN1_15_
Net: DATAIN[15] DATAIN_15_
Net: DIN1[16] DIN1_16_
Net: DATAIN[16] DATAIN_16_
Net: DIN1[17] DIN1_17_
Net: DATAIN[17] DATAIN_17_
Net: DIN1[18] DIN1_18_
Net: DATAIN[18] DATAIN_18_
Net: DIN1[19] DIN1_19_
Net: DATAIN[19] DATAIN_19_
Net: DIN1[20] DIN1_20_
Net: DATAIN[20] DATAIN_20_
Net: DIN1[21] DIN1_21_
Net: DATAIN[21] DATAIN_21_
Net: DIN1[22] DIN1_22_
Net: DATAIN[22] DATAIN_22_
Net: DIN1[23] DIN1_23_
Net: DATAIN[23] DATAIN_23_
Net: DIN1[24] DIN1_24_
Net: DATAIN[24] DATAIN_24_
Net: DIN1[25] DIN1_25_
Net: DATAIN[25] DATAIN_25_
Net: DIN1[26] DIN1_26_
Net: DATAIN[26] DATAIN_26_
Net: DIN1[27] DIN1_27_
Net: DATAIN[27] DATAIN_27_
Net: DIN1[28] DIN1_28_
Net: DATAIN[28] DATAIN_28_
Net: DIN1[29] DIN1_29_
Net: DATAIN[29] DATAIN_29_
Net: DIN1[30] DIN1_30_
Net: DATAIN[30] DATAIN_30_
Net: DIN1[31] DIN1_31_
Net: DATAIN[31] DATAIN_31_
Net: DM[0] DM_0_
Net: DM[1] DM_1_
Net: DM[2] DM_2_
Net: DM[3] DM_3_
Net: RESET_N RESET_N
Net: DQM[0] DQM_0_
Net: DM1[0] DM1_0_
Net: DQM[1] DQM_1_
Net: DM1[1] DM1_1_
Net: DQM[2] DQM_2_
Net: DM1[2] DM1_2_
Net: DQM[3] DQM_3_
Net: DM1[3] DM1_3_
Net: CLK CLK
Net: VCC VCC
Net: GND GND
EndView sdr_data_path sdr_data_path